National Taiwan University Dept Elect EngnTsai, Jeng-LiangJeng-LiangTsaiChen, Charlie Chung-PingCharlie Chung-PingChenChen, GuoqiangGuoqiangChenGoplen, BrentBrentGoplenQian, HaifengHaifengQianZhan, YongYongZhanKang, Steve Sung-MSteve Sung-MKangWong, Martin D.F.Martin D.F.WongSapatnekar, Sachin S.Sachin S.Sapatnekar2006-11-142018-07-062006-11-142018-07-062006-08http://ntur.lib.ntu.edu.tw//handle/246246/200611150121559Dramatic rises in the power consumption and integration density of contemporary systems-on-chip (SoCs) have led to the need for careful attention to chip-level thermal integrity. High temperatures or uneven temperature distributions may result not only in reliability issues, but also timing failures, due to the temperature-dependent nature of chip time-to-failure and delay, respectively. To resolve these issues, high-quality, accurate thermal modeling and analysis, and thermally oriented placement optimizations, are essential prior to tapeout. This paper first presents an overview of thermal modeling and simulation methods, such as finite-difference time domain, finite element, model reduction, random walk, and Green-function based algorithms, that are appropriate for use in placement algorithms. Next, two-dimensional and threedimensional thermal-aware placement algorithms such as matrix-synthesis, simulated annealing, partition-driven, and force directed are presented. Finally, future trends and challenges are described.application/pdf789577 bytesapplication/pdfzh-TWPhysical designplacementthermal analysisthermal simulationjournal articlehttp://ntur.lib.ntu.edu.tw/bitstream/246246/200611150121559/1/136.pdf