Lee, C.-Y.C.-Y.LeeHsieh, P.-H.P.-H.HsiehCHIA-HSIANG YANG2018-09-102018-09-102016http://www.scopus.com/inward/record.url?eid=2-s2.0-84953331618&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/396579This paper presents an energy-recycling micro-architecture and the associated adiabatic logic for ultra-low energy applications, such as implantable bioelectronics. The proposed design achieves low power by transferring and recycling energy between digital logic blocks along with the signal propagation. The CMOS-like layout methodology allows the adiabatic logic core to be synthesized and auto-placed-and-routed with current EDA tools for complex digital systems. A 50% energy saving can be achieved for up to 100 MHz compared to conventional static CMOS logic. As a proof of concept, a 14-tap 8-bit finite impulse response (FIR) filter has been implemented in 90-nm CMOS for implantable neural signal processing. With only 16% area overhead compared to the static CMOS counterpart, the proposed design achieves 70% to 53% of energy reduction for 87 kHz to 410 kHz from a 1 V supply. The FIR filter realized with the proposed energy-recycling logic achieves an FoM of 5.33 nW/MHz/Tap/In-bit/Coeff-bit, yielding a 1.9× to 42× higher energy efficiency than the state-of-the-art custom energy-efficient FIR designs. © 2016 IEEE.Adiabatic logic; CMOS integrated circuits; energy recycling; power minimization[SDGs]SDG7CMOS integrated circuits; Computer architecture; Energy efficiency; FIR filters; Impulse response; Integrated circuit design; Recycling; Signal processing; Adiabatic logic; Energy recycling; Energy reduction; Micro architectures; Neural signal processing; Power minimization; Signal propagation; Standard cell design; Computer circuitsjournal article10.1109/TCSI.2015.2510620