汪重光臺灣大學：電子工程學研究所姚 崴Yao, WeiWeiYao2007-11-272018-07-102007-11-272018-07-102004http://ntur.lib.ntu.edu.tw//handle/246246/57625近年來隨著網際網路的蓬勃發展，使用者對頻寬的需求也日益增加，各種寬頻存取的技術與研究也應運而生，超高速數位用戶迴路(VDSL)技術乃利用固有的電話線路來達到寬頻存取，為其中一種十分經濟且具潛力的解決方案，其高速的傳輸率可有效因應未來高頻寬的需求，並可望取代目前較普及的非對稱數位用戶迴路(ADSL)技術成為下一世代寬頻網路的主流。 本論文為設計並實現一個適用於ANSI T1E1委員會所提出的以單一載波調變的超高速數位用戶迴路傳輸系統，包括傳送機與接收機。首先闡述了關於超高速數位用戶迴路之標準及傳輸通道模型，隨後並提出了基頻傳送機及接收機的架構。在發送端，訊號經過李德-所羅門編碼器(Reed-solomon encoder)等弁鈰炩臛B理後，使用一個正交振幅調變(QAM)器來調變訊號並符合發射必v頻譜遮罩；在接收端，則使用QAM解調器來解調，而為了解決信號在有限頻寬通道傳送時受到的信號間干擾(ISI)，採用一套非全信號週期之可適性等化器(Fractionally spaced adaptive equalizer)來消除這嚴重的干擾，等化器在起始時使用盲目等化法(Blind equalizer)，其利用實際傳輸的資料來更新數位等化器的參數，藉由最小均方誤差法(LMS algorithm)，等化器可以提供足夠的信號雜訊比(SNR)。此外，一個符元率之全數位式時序回復電路(All digital timing recovery)用來調整類比數位轉換器(ADC)之最佳相位，其中包含一個數位控制式震盪器(DCO)。 在硬體實現部分，我們首先使用了Altera公司的FPGA開發平台(Stratix EP1S80 DSP development board)配合Quartus II軟體來達成高效率的系統硬體驗證。最後整個晶片的實現是使用0.18μm CMOS製程，其面積約為3.5x3.5 mm2，在1.8伏特的操作電壓下消耗必v約為175mW。Contents Abstract i Contents iii List of Figures vi List of Tables xi 1. Introduction 1 1.1 Motivation 1 1.2 DSL System Overview 2 1.2.1 Voice band Modems and DSLs 3 1.2.2 Very-high-bit-rate DSL 6 1.3 Modulation Schemes Comparison 8 1.3.1 CAP/QAM vs DMT 8 1.3.2 VDSL Olympics 12 1.4 Thesis Organization 13 2. The SCM-based VDSL Transceiver Architecture 15 2.1 VDSL Specifications 15 2.2 Transmitter Architecture 20 2.3 Twisted-pair Transmission Channel and Noise 21 2.3.1 Channel Model 22 2.2.2 Background Noise 24 2.3.3 Crosstalk Noise 24 2.3.4 Impulse Noise 26 2.3.5 Narrowband Radio Interference 26 2.3.6 Power Spectral Density Comparison of Interferences 32 2.4 Receiver Architecture 33 3. Forward Error Correction and Modulation 35 3.1 Scrambler 35 3.2 Reed-solomon Error Correction Code 37 3.3 Convolutional Interleaver 44 3.4 QAM Modulation 46 3.5 Square-root Raised-cosine Filter 48 3.6 Simulation Results 51 4. Adaptive Blind Equalizer Algorithm and Architecture 53 4.1 Introduction 53 4.2 Equalizer Architecture 54 4.2.1 Linear Equalizer 55 4.2.2 Fractionally Spaced Equalizer 57 4.2.3 Decision-feedback Equalizer 59 4.3 Adaptive Algorithms 60 4.3.1 Zero-forcing Algorithm 61 4.3.2 Least Mean Square Algorithm 61 4.3.3 Blind Adaptive Algorithms 63 4.4 Proposed Pipelined Adaptive Equalizer 65 4.5 Simulation Results 68 5. Timing Recovery Algorithm and Architecture 75 5.1 Review of Timing Recovery Problem 75 5.2 Categorization of Timing Recovery Algorithm 77 5.2.1 Open loop Synchronizer 78 5.2.2 Closed loop Synchronizer 79 5.2.3 Spectral Line Generating Synchronizer 80 5.3 Timing Error Extraction Algorithm 81 5.3.1 Data-aided (DA) Early-late Timing Extraction 81 5.3.2 Decision-directed (DD) Early-late Timing Extraction 83 5.3.3 Non-Data-Aided (NDA) Timing Extraction 83 5.4 Phase-Locked Loop 84 5.4.1 Basic Principles of Phase-locked Loop 85 5.4.2 Discrete-time Model of PLL 90 5.5 Timing Recovery Architecture Analysis 92 5.6 Interpolator 94 5.6.1 Interpolator Fundamentals 94 5.6.2 Limitations of Interpolation 97 5.7 Digitally Controlled Oscillator 100 5.7.1 Divider/Accumulator-based DCO 100 5.7.3 Path Delay Ring Oscillator 103 5.7.4 Delay-line-based DCO 105 5.8 Design of the All Digital Timing Recovery Loop 107 5.8.1 Phase Detector 107 5.8.2 Loop Filter 108 5.8.3 Digitally Controlled Oscillator 110 5.9 Simulation Results 113 6. FPGA Implementation and Measurement Results 117 6.1 Introduction to FPGA 117 6.2 FPGA Design Flow 119 6.3 System Finite Word-length Requirement 120 6.4 FPGA Implementation Platform 123 6.4.1 Software Platform 123 6.4.2 Hardware Platform 124 6.5 Transceiver Hardware 126 6.6 Simulation Results 131 6.6.1 Verilog Simulation Results 131 6.6.2 Quartus II Simulation Results 132 6.7 Measurement Results 133 6.7.1 Measurement Environment 133 6.7.2 Transmitter Measurement Result 135 6.7.3 Receiver Measurement Result 136 6.7.4 Summary 137 7. VLSI Implementation and Chip Verification 139 7.1 ASIC Design Flow 139 7.2 Summary 140 7.2.1 Chip Layout 140 7.2.2 Chip Summary 141 8. Conclusions 143 Appendix 145 A. Introduction to Alteraen-US傳收機超高速數位用戶迴路單一載波調變數位基頻Single CarrierVDSLBaseband Transceiverthesis