Chen, Yen YuYen YuChenWu, Hao YuHao YuWuHUI-RU JIANGCHENG-HONG TSAIWu, Chien ChengChien ChengWu2024-04-172024-04-172024-03-129798400704178https://scholars.lib.ntu.edu.tw/handle/123456789/641952Register clustering is an effective technique for suppressing the increasing dynamic power ratio in modern IC design. By clustering registers (flip-flops) into multi-bit flip-flops (MBFFs), clock circuitry can be shared, and the number of clock sinks and buffers can be lowered, thereby reducing power consumption. Recently, the use of mixed-driving strength MBFFs has provided more flexibility for power and timing optimization. Nevertheless, existing register clustering methods usually employ evenly distributed and invariant path slack strategies. Unlike them, in this work, we propose a register clustering algorithm with slack redistribution at the post-placement stage. Our approach allows registers to borrow slack from connected paths, creates the possibility to cluster with neighboring maximal cliques, and releases extra slack. An adaptive interval graph based on the red-black tree is developed to efficiently adapt timing feasible regions of flip-flops for slack redistribution. An attraction-repulsion force model is tailored to wisely select flip-flops to be included in each MBFF. Experimental results show that our approach outperforms state-of-the-art work in terms of clock power reduction, timing balancing, and runtime.clock power | multi-bit flip-flops | register clustering | timing[SDGs]SDG7conference paper10.1145/3626184.36333272-s2.0-85188463832https://api.elsevier.com/content/abstract/scopus_id/85188463832