Maikap, S.S.MaikapMING-HAN LIAOYuan, F.F.YuanLee, M.H.M.H.LeeHuang, C.-F.C.-F.HuangChang, S.T.S.T.ChangCHEE-WEE LIU2019-03-112019-03-11200401631918https://scholars.lib.ntu.edu.tw/handle/123456789/404466https://www.scopus.com/inward/record.uri?eid=2-s2.0-21644463595&doi=10.1109%2fIEDM.2004.1419117&partnerID=40&md5=dadd58b44b7d41cd6e5ca3cf93d662e4The hole mobility enhancement can be as high as -18% for SiO2 and ∼20% for high-κ HfO2 gate stack dielectrics with the uniaxial compressive strain (0.2%) parallel to the channel. The highest drain current of -22% at saturation and ∼30% at linear region is observed for the bulk Si PMOS with high-K gate stacks. The drain current and hole mobility of bulk Si PMOS are degraded under the small biaxial tensile strain, while substrate-strained Si device shows opposite. The nonoptimized ring oscillator has the speed enhancement of ∼7% under the uniaxial tensile strain parallel to NMOS channel. Proper package strain also gives the drive-current as well as mobility enhancement at 100°C. © 2004 IEEE.Hafnium oxides; High-k dielectric; Hole mobility; Logic gates; Silica; Silicon; Tensile strain; Timing circuits; VLSI circuits; Annealing; Dielectric materials; Doping (additives); Hole mobility; Silicon wafers; Surface roughness; Circuit performance; Compressive strain; Device performance; Drain holes; High-K gate stacks; High-κ; Linear region; Mobility enhancement; Package strain; Uniaxial compressive; Drain current; MOSFET devices; Compressive stain; Dopants; Tensile strain; Thermal budgetconference paper10.1109/IEDM.2004.14191172-s2.0-21644463595