臺灣大學: 電子工程學研究所劉深淵呂健豪Lu, Jian-HaoJian-HaoLu2013-04-102018-07-102013-04-102018-07-102010http://ntur.lib.ntu.edu.tw//handle/246246/257036隨著製程技術的日新月異，處理器和記憶體的操作頻率快速地增加。這使得輸入/輸出介面的頻寬變成在眾多系統中主要的瓶頸。例如在有線通訊系統中，高速資料傳輸就同時遭受到集膚效應和介質損耗。這些和頻率相關的損害導致嚴重的符際干擾進而毀損傳輸的資料，也因此惡化了位元錯誤率。為了減輕符際干擾並改善位元錯誤率，類比等化器已經被廣泛的應用於通道損耗的補償。然而，在最新的寬頻資料通訊中，當多通道串接變得更加靠近時，傳輸的資料也另外遭受到干擾擾亂的損害。 本論文主要分成兩個部份。首先，介紹應用於有線通訊系統之高速類比等化器。其次，介紹一應用於有線通訊系統，特別是針對多通道串接式接收機之數位式近端干擾消除電路。在第二章中，利用所提出之連續主動式回授架構，可以在0.13微米CMOS製程下實現一10-Gb/s無電感之類比等化器。在第三章中，利用所提出之電感式回授放大器，可以在0.13微米CMOS製程下實現一40-Gb/s、14.4毫瓦之類比等化器。在第四章中，利用所提出之變壓器回授技術，可以在65奈米CMOS製程下實現一50-Gb/s、10毫瓦之類比等化器。在第五章中，利用所提出之sign-sign block least-mean-square (SSB-LMS)電路，可以在0.13微米CMOS製程下實現一5-Gb/s數位式近端干擾消除電路與類比等化器之混合電路。 利用所提出之電感式回授放大器實現之類比等化器是第一個40-Gb/s在0.13微米CMOS製程下實現的。而利用所提出之SSB-LMS電路，對於5-Gb/s的資料速率，上/下計數器之最大關鍵延遲時間可以放寬至500皮秒，有別於原來的200皮秒。As process technologies continue to advance, the operating frequency of processors and memories increases rapidly. This makes the bandwidth of the I/O interface a primary bottleneck in many systems. For example, high-speed data transmission in a wireline communication system suffers from both skin effect and dielectric loss. These frequency-dependent impairments induce a significant inter-symbol interference (ISI) to corrupt the transmitted data and therefore degrade the bit error rate (BER). In order to mitigate the ISI and ameliorate the BER, analog equalizers have been used widely so as to compensate the channel loss. In modern broadband data communications, however, the transmitted data are also impaired by crosstalk interferences when multi-lane serial links become closer. This dissertation is mainly divided into two parts. High-speed analog equalizers for wireline communication systems are introduced first, followed by a digital near-end crosstalk (NEXT) canceller, especially for multi-lane serial-link receivers. In chapter 2, a 10-Gb/s inductorless analog equalizer is realized in 0.13-μm CMOS technology by using the proposed interleaved active feedback topology. In chapter 3, a 40-Gb/s 14.4-mW analog equalizer is realized in 0.13-μm CMOS technology by using the proposed inductive feedback amplifier. In chapter 4, a 50-Gb/s 10-mW analog equalizer is realized in 65-nm CMOS technology by using the proposed transformer feedback technique. In chapter 5, a 5-Gb/s digital NEXT canceller merged with an analog equalizer is realized in 0.13-μm CMOS technology by using the proposed sign-sign block least-mean-square (SSB-LMS) circuit. The analog equalizer using the proposed inductive feedback amplifier is the first 40-Gb/s one in 0.13-μm CMOS technology. By using the proposed SSB-LMS circuit, the maximum critical delay of the up/down counters is relaxed to 500 ps rather than 200 ps for the data rate of 5-Gb/s.7752632 bytesapplication/pdfen-US類比等化器數位式近端干擾消除電路Analog EqualizerDigital Near-End Crosstalk Cancellerthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/257036/1/ntu-99-D93943005-1.pdf