盧信嘉臺灣大學：電子工程學研究所楊子承Yang, Tz-ChengTz-ChengYang2007-11-272018-07-102007-11-272018-07-102006http://ntur.lib.ntu.edu.tw//handle/246246/57485隨著無限通訊系統的快速發展，對於具有高精確度鎖相迴路的需求也 隨著顯著增加。不僅如此，在鎖相迴路中的輸出相位雜訊對本地震盪器而 言是一個非常重要的性能指標，因為相位雜訊的好壞會影響到整體接收訊 號的品質。相位雜訊差，將會干擾到鄰近通道的訊號產生嚴重的收發問題。 本篇論文的目標即在實現一個適用於40~48 GHz超寬頻系統的低相位 雜訊18.5 GHz鎖相迴路。除了一個常見的高速架構外，我們也會提出一個 使用全差動頻率相位偵測器的改良型鎖相迴路，並且將會探討兩者間的性 能差異。With the rapid growing of the wireless communication system, the demands of high precision phase-locked loops (PLLs) increase significantly. Besides, output phase noise of PLLs is very important for local oscillator. It is because that the quality of phase noise would influence bith transmitting and receiving chain seriously. This thesis will aim to implement an 18.5 GHz PLL with improved phase noise for 40~48 GHz UWB system. We will propose two architectures which are a common high speed phase-locked loop and an improved fully differential phase-locked loop. The performance of both architectures will be compared.Chapter 1 Introduction 1 1.1 Ultra-Wideband Overview 2 1.2 Motivation and Research Goals 6 1.3 Thesis Overview 7 Chapter 2 Phase-Locked Loops Fundamentals 9 2.1 Phase-Locked Loops Basics 9 2.2 Type-Order 13 2.3 Error Constants 13 2.4 Stability 16 2.5 Bandwidth 22 2.6 Phase-Locked Loops Performance 22 2.6.1 Phase Noise 23 2.6.2 Spurs 25 2.6.3 Lock Time 27 2.6.4 Loop Bandwidth 28 2.6.5 Fastlock 28 2.6.6 RMS Phase Error 29 Chapter 3 Circuit Architecture and Implementation 33 3.1 Phase/Frequency Detector 33 3.2 Charge Pump 41 3.3 Loop Filter 44 3.4 Frequency Divider 50 3.4.1 Miller Divider 51 3.4.2 CML Master-Slave DFF Static Divider 56 3.5 Differential to Single-ended Converter 60 3.6 VCO 61 3.7 PLL Closed-Loop Simulation 62 3.8 Layout and Floorplan 65 Chapter 4 An Improved Fully Differential Phase-Locked Loop 67 4.1 A Differential-Type Phase Frequency Detector 68 4.2 VCO 76 4.3 Fully Differential PLL Closed-Loop Simulation 77 4.4 Layout and Floorplan 81 Chapter 5 Test and Measurement 83 5.1 Measurement Configuration of PLL With Air Cavity Resonator 84 5.2 Measurement Configuration of PLL with LTCC Cavity Resonator 85 5.3 Measurement Procedures 86 Chapter 6 Conclusion 87 Reference 8910411049 bytesapplication/pdfen-US差動鎖相迴路超寬頻相位雜訊PLLUWBdifferentialphase noisejitterthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57485/1/ntu-95-R92943062-1.pdf