SoC test scheduling using the B*-tree based floorplanning technique

Dept. of Electr. Eng., National Taiwan Univ.Wuu, Jen-YiJen-YiWuuChen, Tung-ChiehTung-ChiehChenChang, Yao-WenYao-WenChang2007-04-192018-07-062007-04-192018-07-062005-01http://ntur.lib.ntu.edu.tw//handle/246246/200704191001522http://ntur.lib.ntu.edu.tw/bitstream/246246/200704191001522/1/01466554.pdfapplication/pdf918472 bytesapplication/pdfen-US[SDGs]SDG11SoC test scheduling using the B*-tree based floorplanning techniquejournal article10.1109/ASPDAC.2005.1466554http://ntur.lib.ntu.edu.tw/bitstream/246246/200704191001522/1/01466554.pdf