Chou YHsu J.-WChen T.-C.YAO-WEN CHANG2022-04-252022-04-2520210738100Xhttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85119423062&doi=10.1109%2fDAC18074.2021.9586294&partnerID=40&md5=85997d79c34585e55c89b3b51f5f01e5https://scholars.lib.ntu.edu.tw/handle/123456789/607516AI-dedicated hardware designs are growing dramatically for various AI applications. These designs often contain highly connected circuit structures, reflecting the complicated structure in neural networks, such as convolutional layers and fully-connected layers. As a result, such dense interconnections incur severe congestion problems in physical design that cannot be solved by conventional placement methods. This paper proposes a novel placement framework for CNN accelerator units, which extracts kernels from the circuit and insert kernel-based regions to guide placement and minimize routing congestion. Experimental results show that our framework effectively reduces global routing congestion without wirelength degradation, significantly outperforming leading commercial tools. ? 2021 IEEE.Convolutional neural networksMultilayer neural networksTraffic congestionVLSI circuitsAI applicationsCircuit structuresComplicated structuresConvolutional neural networkDedicated hardwareHardware designNeural-networksRouting congestionStructure-awareVLSI structuresConvolution[SDGs]SDG9conference paper10.1109/DAC18074.2021.95862942-s2.0-85119423062