楊佳玲臺灣大學：資訊工程學研究所紀兆韋Chi, Jaw-WeiJaw-WeiChi2007-11-262018-07-052007-11-262018-07-052006http://ntur.lib.ntu.edu.tw//handle/246246/54047隨著科技的進步, 記憶體漏電的問題越來越備受重視. 因為快取記憶體佔住處理器上大部分的面積, 各種研究專注於處理快取記憶體上的漏電問題.有兩種電路設計專門降低記憶體上的漏電, 分別是GatedVdd以及Drowsy cache.漏電的控制方法有週期性的把Cache lines放入低漏電模式, 或是當一條cache line經過一段時間沒有被存取時, 才放入低漏電模式.然而這兩種方法並沒有考慮到Cache line狀態的轉換所造成的延遲.控制方法所形成的延遲使得執行時間的延長, 因此這兩種方法不適需要在時限內取得正確執行結果的硬性合即時系統.在這篇論文中, 我提出了針對硬性即時系統所設計的漏電控制方法. 我利用程序內以及程序之間的閒置時間來彌補Cache line狀態的轉換所造成的延遲.新漏電控制方法的目標是在不違反時限下達到省電的目的.根據實驗模擬的結果顯示出, 所提出的控制方法可以檢少85.2%的漏電,並且保證即時系統下的程序都能在時限內完成工作.Leakage energy consumption is an increasing important issue as the technology continues to shrink. Since on-chip caches constitute a major portion of the processor's transistor budget, they are the primary targets for processor leakage reduction. Two types of circuit techniques have been proposed to reduce cache leakage: Gated-Vdd and drowsy caches. Cache lines can be turned into a low-leakage state periodically or being idle for a pre-set number of cycles. Both control policies induce performance unpredictability thereby not suitable for real-time applications. In this thesis, I propose a cache leakage control algorithm for hard real-time applications. I exploit task slack to turn cachelines into the low leakage state. The objective of the proposed algorithm is to achieve leakage reduction while meeting the timing constraint. The proposed scheme can achieve 85.2\% leakage reduction on average while meeting the real-time constraint.Abstract i 1 Introduction 1 2 Background 4 2.1 Source of leakage power consumption . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Circuit techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2.1 State-destructive circuit . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2.2 State-preserving circuit techniques . . . . . . . . . . . . . . . . . . . 8 2.3 Leakage Control Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Worst case execution time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Leakage control policy 11 3.1 System model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Preprocess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.1 Static slack allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.2 Worst case active set analysis . . . . . . . . . . . . . . . . . . . . . . 16 3.3 Active task leakage control policy . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1 Dynamic slack reclaiming . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.2 WCAS-based drowsy window resizing . . . . . . . . . . . . . . . . . . 21 3.3.3 PAS-based drowsy window resizing . . . . . . . . . . . . . . . . . . . 24 3.4 Idle task leakage control policy . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.1 Performance overhead of low leakage mode . . . . . . . . . . . . . . . 28 3.4.2 Slack and energy modelling for idle task . . . . . . . . . . . . . . . . 29 3.4.3 Deciding low leakage mode for idle task . . . . . . . . . . . . . . . . . 31 4 Experiment results 32 4.1 Experiment setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2 Miss ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3 Leakage saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.4 Runtime CPU utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.5 Cache design space exploration . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5.1 Block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5.2 Cache size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5.3 Associativity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.5.4 Conclusion of cache design space exploration . . . . . . . . . . . . . . 47 5 Related work 48 6 Conclusion 51680769 bytesapplication/pdfen-US快取記憶體漏電流即時系統CacheLeakageReal time system[SDGs]SDG7thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/54047/1/ntu-95-R93922054-1.pdf