賴飛羆Lai, Fei-Pei臺灣大學:電機工程學研究所陳韋綸Chen, Wei-LunWei-LunChen2010-07-012018-07-062010-07-012018-07-062009U0001-2707200902491700http://ntur.lib.ntu.edu.tw//handle/246246/188167本論文提出一種新穎的電路架構設計，用以實現高速度與低功率的內容可定址記憶體。內容可定址記憶體目前已被廣泛的應用於許多數位系統，尤其是網路路由器的應用，且為了滿足其高速搜尋比對的需求，通常內容可定址記憶體都採用平行比對的機制來維持高速運作的特性，但也造成相當高的功率消耗。 因此，我們提出一個低電壓擺幅概念的電路以取代傳統可定址記憶體單元，主要目的在於降低匹配線的電壓擺幅，藉由匹配線上充放電的電壓擺幅縮減，使得每次運算周期的充放電流大幅減少，有效的降低功率消耗，且額外的提升操作速度；並針對匹配線感測放大器重新作電路架構設計，避免因匹配線擺幅縮減而造成輸出邏輯錯誤。最後，利用台積電0.18製程技術來模擬整體功率消耗情形，測量得知提出的記憶體單元大約可降低35%的功率消耗，並且可以作為廣泛的應用。This thesis presents a novel VLSI architecture for high speed and low power content addressable memory (CAM) design. CAMs have been widely used in many digital systems. The primary application of CAMs is network routers, that requiring high search speed. Therefore CAMs usually are used in parallel design to maintain the property of high speed operation, but also resulted in serious power consumption.n order to solve the problem, we propose a low voltage swing cell circuit to replace traditional CAM cell. The main purpose is to reduce the matchline voltage swing. Because of charge/discharge voltage swing reduction on the matchline, the charge/discharge current will be reduced during operation cycle. The proposed design can reduce power consumption effectively, in addition to increase the performance. We also design new matchline sense amplifier to avoid the output logic error caused by low swing of the matchline. Finally, we used TSMC 0.18um CMOS technique to simulate the proposed CAM cell. For the proposed structures, the power consumption will be reduced about 35% and have a general and robust application.口試委員會審定書........................................I謝...................................................II文摘要..............................................IIIbstract...............................................IVontents................................................Vist of Figures.......................................VIIist of Tables.........................................IXhapter 1 Introduction.................................1 1.1 Low Power Requirement............................1 1.2 Power Consumption of CMOS Circuit................2 1.2.1 Static Power Consumption....................2 1.2.2 Dynamic Power Consumption...................6 1.3 Organization of the Thesis......................11hapter 2 An Overview of CAM..........................12 2.1 Conventional CAM Architecture...................12 2.2 Conventional CAM Cell...........................15 2.3.1 NOR-Type CAM Cell..........................15 2.3.2 NAND-Type CAM Cell.........................17 2.3.2 Ternary CAM Cell...........................18 2.3 Match-Line Structure............................20 2.3.1 NOR-Type Match-Line........................20 2.3.2 NAND-Type Match-Line.......................22 2.4 CAM Application.................................24 2.4.1 Cache Memory...............................24 2.4.2 Translation Look-aside Buffer..............26 2.4.3 Network Router.............................27hapter 3 Proposed CAM................................30 3.1 Proposed CAM Architecture.......................30 3.2 Low Voltage Swing Technique.....................32 3.2.1 Match Condition............................33 3.2.2 Mismatch Condition.........................34 3.3 Improvement on the Proposed CAM Cell............35 3.4 Matchline Sense Amplifier.......................37hapter 4 Simulation Results..........................40 4.1 Proposed CAM Simulation Result..................40 4.2 Improved CAM Simulation Result..................44 4.3 Comparison Table................................48hapter 5 Conclusion..................................50eference..............................................511439554 bytesapplication/pdfen-US內容可定址記憶體低功率低電壓擺幅CAMLow PowerLow Voltage Swingthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/188167/1/ntu-98-R96943158-1.pdf