Chao-Ching HungSHEN-IUAN LIU2018-09-102018-09-102011-0315497747http://scholars.lib.ntu.edu.tw/handle/123456789/366437https://www.scopus.com/inward/record.uri?eid=2-s2.0-79952936056&doi=10.1109%2fTCSII.2011.2110390&partnerID=40&md5=872b2405561d904642c17e3a838013efA noise filtering technique for fractional-N frequency synthesizers (FNFSs) is presented. The noise filter is based on an integer-N (N = 1) phase-locked loop that is placed in a feedback path of an FNFS. By adopting the noise filter, out-of-band quantization noise of a high-order deltasigma modulator is suppressed. In addition, folded noise due to nonlinearity of a phase/frequency detector (PFD) and a charge pump is improved by reducing phase errors at PFDs. An FNFS using the noise filter is fabricated in 90-nm complementary metaloxidesemiconductor technology. Its die area is 950 by 950 μm, and its power consumption is 30 mW for a supply voltage of 1 V. The frequency resolution of this FNFS is less than 1 Hz. © 2006 IEEE.Folded noise; frequency synthesizer; quantization noise filteringFrequency synthesizers; Delta sigma modulator; Folded noise; Fractional-N frequency synthesizers; Frequency resolutions; Noise filtering; Phase/frequency detector; Quantization noise; Supply voltages; Phase noisejournal article10.1109/TCSII.2011.21103902-s2.0-79952936056WOS:000288457200003