A bipartition-codec architecture to reduce power in pipelined circuits

Dept. of Electr. Eng., National Taiwan Univ.Ruan, Shanq-JangShanq-JangRuanShang, Rung-JiRung-JiShangLai, FeipeiFeipeiLaiChen, Shyh-JongShyh-JongChenHuang, Xian-JunXian-JunHuang2007-04-192018-07-062007-04-192018-07-061999-11http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021563application/pdf625900 bytesapplication/pdfen-USA bipartition-codec architecture to reduce power in pipelined circuitsjournal article10.1109/ICCAD.1999.810627http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021563/1/00810627.pdf