張家歐臺灣大學:應用力學研究所劉世宇Liu, Shih-YuShih-YuLiu2010-05-182018-06-292010-05-182018-06-292009U0001-0608200919384000http://ntur.lib.ntu.edu.tw//handle/246246/183573本論文的主旨是探討CMOS微型位移電容感測器之輸出電壓與電容改變量的關係，在實現CMOS位移電容感測器之佈局圖後，將此佈局圖下線並做出實體晶片，接著量測此晶片並分析各節點訊號，進一步討論內部元件運作情形是否正常。本晶片主要是用摺疊疊接式放大器做為主體，接著佈局離散元件，最後接上pad完成佈局圖，下線做出實體晶片後加以量測並改正。 本論文使用國家晶片系統設計中心(NSC Chip Implementation Center, CIC )所提供的台灣積體電路(TSMC)0.35微米 Mixed-Signal 2P4M Polycide3.3/5V的製程，並使用Synopsys公司出的Hspice電路模擬軟體與思源公司的laker軟體進行模擬及佈線。The theme of the thesis is to discuss the relation of the output voltage and the variance of capacitance about CMOS displacement capacitive sensors. Design and completion of the layout is the first step of the procedure flow. According to the layout the IC is taped out. The last step is to measure and to analyze the signals from every nodes. Through the whole procedure flow, the components which are workable can be defined. This circuit is composed of folded-cascode amplifiers and dispersed elements. The chip can be measured after taping out the IC. In this thesis, we apply 0.35 Mixed-Signal 2P4M Polycide 3.3/5V manufacture process of TSMC which is provided by NSC Chip Implementation Center. Finally, we use Hspice software designed by Synopsys co. to simulate and laker software designed by Springsoft co. to layout the circuit.口試委員會審定書..................................................................................................i謝...................................................................................................................ii文摘要...................................................................................................iii文摘要..............................................................................................................iv錄..................................................................................................................v目錄............................................................................................................viii目錄..........................................................................................................xiii一章 導論.....................................................................................................1.1研究背景..............................................................................................................1.2研究動機..............................................................................................................2.3文獻回顧..............................................................................................................3.4本文目的與章節摘..............................................................................................9二章 環形陀螺儀其振動原理與分析....................................................................10.1環形陀螺儀之原理簡介....................................................................................10.2環形陀螺儀之感測原理.....................................................................................11.3環形陀螺儀架構與電容值的計算....................................................................12.4本論文之架構電容值估算................................................................................14三章 IC佈局設計流程簡介...................................................................................16.1 IC設計流程.......................................................................................................16.2佈局圖設計之考量要素....................................................................................18四章 系統架構與運算放大器佈局與模擬............................................................19.1本論文的架構與性能的模擬............................................................................19.2摺疊疊接式運算放大器主體............................................................................22.2.1摺疊疊接式運算放大器佈局.......................................................................24 4.3寬振幅常數互導偏壓電路................................................................................24 4.4電阻....................................................................................................................25 4.5摺疊疊接式放大器的特性模擬........................................................................29.5.1摺疊疊接式放大器之共模互斥比(CMRR) ................................................294.5.2電源互斥比(PSRR) ......................................................................................314.5.3相位邊界(Phase Margin) ..............................................................................324.5.4迴轉率(Slew Rate) .......................................................................................34五章 離散元件的佈局及模擬................................................................................36.1前言....................................................................................................................36.2互補式開關........................................................................................................36.3無穩態多諧振盪器............................................................................................37.4緩衝器(Buffer) ..................................................................................................42.5 S/H之時脈設計(Clock Design) ........................................................................44.6 MOS電阻的設計...............................................................................................47.7靜電防護pad (ESD pad) ...................................................................................49.8結論....................................................................................................................50六章 晶片及印刷電路板製作及量測流程............................................................51.1晶片設計與製作流程........................................................................................51.2印刷電路板設計與製作流程............................................................................54.3打線....................................................................................................................57.4量測....................................................................................................................59七章 量測與模擬結果比較....................................................................................62.1上端單一放大器之量測與模擬結果比較........................................................62.1.1方波產生器之模擬.......................................................................................63.1.2節點 模擬與量測的圖形比較.................................................................63.1.3節點 模擬與量 測的圖形比較...............................................................65.1.4節點 模擬與量測的圖形比較.............................................................67.1.5節點 模擬與量測的圖形比較............................................................69.1.6上端單一放大器總結論...............................................................................71.2下端單一放大器之模擬與量測結果比較........................................................72.2.1節點 模擬與量測的圖形比較.................................................................72.2.2節點 模擬與量測的圖形比較.................................................................74.2.3節點 模擬與量測的圖形比較.............................................................76.2.4節點 模擬與量測的圖形比較............................................................78.2.5下端單一放大器總結論...............................................................................80.3錯誤檢討及改正................................................................................................81.4緩衝器效能分析....................................................................................86八章 未來展望 ....................................................................................91考文獻...............................................................................................93者簡介.....................................................................................................95application/pdf5948532 bytesapplication/pdfen-US位移電容感測器類比積體電路摺疊疊接式放大器晶片設計佈局capacitive sensoranalog integrated circuitfolded-cascode amplifierIC designlayoutthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/183573/1/ntu-98-R96543061-1.pdf