陳俊良臺灣大學：資訊工程學研究所江盈宏Chiang, Ying-HungYing-HungChiang2007-11-262018-07-052007-11-262018-07-052005http://ntur.lib.ntu.edu.tw//handle/246246/53950隨著 SoC 的流行以及晶片製造技術的進步，嵌入式系統的功能越來越龐大而且上市時間的壓力也越來越緊湊。在這個情況下，為了系統的效能以及更短的生產週期，ASIP (application specific instruction-set processors) 以及硬體架構描述語言 ADL (architecture description language) 的使用是一個必然的趨勢。在每一個硬體架構的評估流程中，必需將應用程式依照新的架構重新編譯並執行以取得效能的測試數據，因此編譯器依照硬體的重新移植變成非常重要的課題。一般的做法是以手動的方式將現有的編譯器重新打造，或者利用可重標地編譯器 (retargetable compiler) 依照硬體描述即時地產生執行檔，但是前者需要大量的人力反覆實作，而後者會使得執行的速度變慢。本論文的目的在於利用 GCC 的可重標地的特性，將硬體的架構描述檔轉換成GCC 移植時所必需提供的機器描述檔 (machine description)，並討論轉換時所遇到的相關問題及限制。最後我們以本論文執行時所遇到的問題提出一些對硬體架構描述語言的建議，可以在未來設計或修改硬體架構描述語言時做為參考。With the popularity of SoC and improvement in IC design, the functionality of embedded system becomes more complex with shorter time-to-market. Under this circumstance, design space exploration using ASIP (application specific instruction-set processor) and ADL (architecture description language) becomes a natural way. On each cycle of exploration, the application has to be recompiled and executed to obtain the profiling result. Therefore, porting compiler according to the ADL becomes an important issue. Currently, porting an existing compiler by human or using a retargetable compiler are general approaches, but require much human resource or slow down the compiling process. In this thesis, we convert ADL description to a GCC's machine description and discuss some problem and limitation. Finally we propose some suggestion for ADL that we encounter in this thesis.摘要 i Abstract iii Contents v List of Figures vii List of Tables ix Listings xi Chapter 1 Introduction 1 1.1 Research Motivation 1 1.2 Related Research 1 1.2.1 Retargetable Compilers 2 1.2.2 Integrating ADL with GCC 4 1.3 Thesis Organization 4 Chapter 2 Architecture Description Language 5 2.1 Functionalities of ADL 5 2.2 EXPRESSION ADL 7 2.2.1 Functionality of EXPRESSION 7 2.2.2 Sections of EXPRESSION 9 2.2.3 Compiler Support of EXPRESSION 10 Chapter 3 GNU Compiler Collection 13 3.1 Passes of the GCC Compiler 13 3.2 Front End: From Source Program to Tree Representation 14 3.3 Middle End: From Tree Representation to RTL Rpresentation 16 3.4 Back End: From RTL Representation to Assembly Generation 17 3.5 Machine Description 18 3.5.1 Format of define_insn and define_expand 18 3.5.2 Example and Discussion 19 3.5.3 Summary of define_insn and define_expand 22 3.6 Porting GCC to a New Architecture 23 Chapter 4 Strategy of the Design 25 4.1 Overall Strategy 25 4.1.1 Cross-Compilation 25 4.1.2 Design Process 26 4.2 Design of MdGen 27 4.3 Design of MdMerger 28 4.4 Applying Scenarios 30 Chapter 5 MdGen Implementation 33 5.1 Overall Structure 33 5.2 Parsing EXPRESSION ADL File 34 5.3 Generation of Name of ‘define_insn’ or ‘define_expand’ 34 5.4 Generation of the RTL-template 35 5.4.1 Main Structure of RTL-template 35 5.4.2 Matching GENERIC Assembly with Standard Name 36 5.4.3 Predicates and Constraints of RTL Template 37 5.5 Generation of the Assembly Output 38 5.6 Generation of the Attribute Settings 38 5.7 Generation of Incomplete Patterns 39 5.8 Generation of Optimization Patterns 40 Chapter 6 MdMerger Implementation 41 6.1 Strategy of MdMerger 41 6.2 Parsing MD Files 41 6.3 Comparison of Two RTXes 42 6.4 Implementation of MdMerger 43 Chapter 7 Verification Setup and Results 45 7.1 Environment Setup 45 7.1.1 Building Assembler and Linker Using Binutils 46 7.1.2 Build a Cross-Compiler Using GCC 46 7.1.3 Build a Simulator 47 7.2 Verification Setup 47 7.3 Verification Result 50 Chapter 8 Proposal for an ADL 53 8.1 Instruction Set Architecture Information 53 8.1.1 Opcode 54 8.1.2 Assembly Format 55 8.1.3 Special Constraint 55 8.1.4 Instruction Semantics 55 8.2 Completeness of Machine Description 57 8.2.1 Minimum Standard Name 57 8.2.2 Completeness of Tree Representation 59 Chapter 9 Conclusion and Future Work 61 9.1 Conclusion 61 9.2 Future Work 61 References 63431268 bytesapplication/pdfen-US編譯器移植GCCASIPcompilerportingthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/53950/1/ntu-94-R92922018-1.pdf