A two-cycle lock-in time ADPLL design based on a frequency estimation algorithm

AN-YEU(ANDY) WUWu, C.-T.C.-T.WuShen, W.-C.W.-C.ShenWang, W.W.WangAN-YEU(ANDY) WU2018-09-102018-09-102010http://www.scopus.com/inward/record.url?eid=2-s2.0-77953727164&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/358395A two-cycle lock-in time ADPLL design based on a frequency estimation algorithmjournal article10.1109/TCSII.2010.2048358