Yang, L.-Y.L.-Y.YangHSIN-SHU CHENYI-JAN EMERY CHEN2018-09-102018-09-10200815311309http://www.scopus.com/inward/record.url?eid=2-s2.0-40549121663&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/340736https://www.scopus.com/inward/record.uri?eid=2-s2.0-40549121663&doi=10.1109%2fLMWC.2008.916812&partnerID=40&md5=c97b2a06abf23696c3eaf9e8bd80847bThis letter presents the first CMOS Doherty power amplifier (PA) fully integrated on chip. The "cascode-cascade" amplifier architecture is proposed to get rid of the bulky power splitter and facilitate the integration. The quarter wavelength transmission lines are replaced by the lumped component networks such that the whole amplifier circuit can be squeezed into the die size of 1.97 × 1.4 mm2. Fabricated in 0.18 μm CMOS technology, the 3.3 V PA achieves 12 dB power gain. The measured output power and power added efficiency (PAE) at P1 dB are more than 21 dBm and 14%, respectively. The PAE at 7 dB back-off from P1 dB is above 10% and the PAE degradation is less than 29%. © 2008 IEEE.CMOS; Efficiency; Fully integrated; Orthogonal frequency division multiplexing (OFDM); Peak-to-average power ratio (PAPR); Power amplifier (PA); Power back-offElectric lines; Integration; Microprocessor chips; Networks (circuits); Power amplifiers; Amplifier circuit; Quarter wavelength transmission lines; CMOS integrated circuitsjournal article10.1109/LMWC.2008.9168122-s2.0-40549121663