電機資訊學院: 電子工程學研究所指導教授: 李泰成鄭伊涵Cheng, Yi-HanYi-HanCheng2017-03-062018-07-102017-03-062018-07-102014http://ntur.lib.ntu.edu.tw//handle/246246/276356本論文提出降低震盪器相位雜訊之頻率合成器。藉著開迴路延遲的相位雜訊小於閉迴路相位雜訊的特性，利用開迴路延遲改善環型振盪器的相位雜訊。提出的鎖相迴路能夠對高於頻寬的環形振盪器相位雜訊進行抑制。使用0.18μm製程，32k 赫茲的輸入訊號，輸出為1G赫茲的鎖相迴路在100k赫茲為-83dBc/Hz的相位雜訊，改善了10dB。此頻率合成器在1.8伏特供應電壓下消耗了17.64毫瓦。A frequency synthesizer with a phase noise reduction technique is presented. By the property that the phase noise of an opened-loop delay is smaller than that of a closed-loop delay, an analog delay line is employed to improve the phase noise of a ring oscillator. The proposed phase-locked loop (PLL) can suppress the noise beyond the PLL loop bandwidth. Fabricated in a 0.18μm CMOS technology, for a 32-kHz input frequency, the 1-GHz PLL with a ring oscillator can generate an output with the phase noise -83 dBc/Hz at a 100-kHz frequency offset, which is more than 10 dB suppression. The clock generator consumes 17.64 mW from a 1.8-V power supply.2424110 bytesapplication/pdf論文公開時間: 2016/2/4論文使用權限: 同意有償授權(權利金給回饋本人)頻率合成器鎖相迴路相位雜訊開迴路延遲閉迴路延遲Frequency synthesizerphase-locked loopphase noiseopened-loop delayclosed-loop delaythesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/276356/1/ntu-103-R01943014-1.pdf