國立臺灣大學電子工程研究所Wei, J.-Y.J.-Y.WeiMaikap, S.S.MaikapLee, M.H.M.H.LeeLee, C.C.C.C.LeeLiu, C.W.C.W.Liu2006-11-142018-07-102006-11-142018-07-102006http://ntur.lib.ntu.edu.tw//handle/246246/2006111501244083Due to the Fermi level pinning effect on the hole confinement at the valence band offset, the capacitance–voltage (C–V) characteristics of NMOS capacitor exhibit more obvious plateau than that of PMOS capacitor, demonstrated by both experimental and simulated results. Using device simulation, the ratio of hole density at the oxide/strained-Si interface to that at the strained-Si/relaxed SiGe interface for both N and PMOSFETs is investigated. The much higher hole density ratio in PMOSFETs than that in NMOSFETs also reveals the Fermi level pinning effect.application/pdf140449 bytesapplication/pdfzh-TWMOS C–VStrainDevice simulationHole confinementPinning effectjournal articlehttp://ntur.lib.ntu.edu.tw/bitstream/246246/2006111501244083/1/1534.pdf