On-chip random jitter testing using low tap-count coarse delay lines

JIUN-LANG HUANG2018-09-102018-09-102006-1209238174http://scholars.lib.ntu.edu.tw/handle/123456789/325750https://www.scopus.com/inward/record.uri?eid=2-s2.0-33846682693&doi=10.1007%2fs10836-006-9444-3&partnerID=40&md5=b96497a1e7a6f7cff289091249e5827eAn on-chip RMS jitter testing technique for design-for-test (DfT) applications is presented in this paper. In addition to utilizing a less complicated low tap-count variable delay line to sample the jitter's cumulative density function (CDF), a sophisticated post-processing algorithm is developed to enhance process variation tolerance. Our simulation results show that using an eight-tap delay line, the probability of making correct pass/fail decisions is higher than 99% in the presence of up to 30% delay line value deviations. © Springer Science + Business Media, LLC 2006.application/pdf429463 bytesapplication/pdfAnalog/mixed-signal testing; Design-for-test; Jitter measurement; Random jitterComputer simulation; Design for testability; Electric delay lines; Microprocessor chips; Probability; Probability density function; Analog/mixed signal testing; Delay line value deviations; Jitter measurement; Random jitters; JitterOn-chip random jitter testing using low tap-count coarse delay linesjournal article10.1007/s10836-006-9444-32-s2.0-33846682693WOS:000243407600009