Chen W.-MYao Y.-SSHEN-IUAN LIU2023-06-092023-06-09202215497747https://www.scopus.com/inward/record.uri?eid=2-s2.0-85118654253&doi=10.1109%2fTCSII.2021.3125103&partnerID=40&md5=fd63601670685d933175f55d44d69456https://scholars.lib.ntu.edu.tw/handle/123456789/632357A digital clock/data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE) and a calibration circuit is presented. This CDR circuit is fabricated in 40-nm CMOS technology and its active area is 0.1 mm2. For a channel loss of -10.31dB at 10GHz and a 20Gb/s PRBS of 27-1 , the measured bit error rate is less than 10-12. By the proposed calibration circuit, the measured high-frequency jitter tolerance is improved. The measured convergence time of the calibration circuit is less than 5μ s. The power of this CDR circuit is 55.4mW at 20 Gb/s, and the calculated energy efficiency is 2.77pJ/b. © 2004-2012 IEEE.Calibration; Decision feedback equalizer; Digital clock and data recovery; Jitter toleranceBit error rate; Clock and data recovery circuits (CDR circuits); Clocks; Decision feedback equalizers; Energy efficiency; Feedback; Jitter; Threshold voltage; Clock and data recovery; Code; Decision-feedback equalizers; Digital clock and data recovery; Digital clocks; Digital datas; Generator; Jitter tolerance; Jitter tolerance.; Calibrationjournal article10.1109/TCSII.2021.31251032-s2.0-85118654253