陳信樹臺灣大學：電子工程學研究所洪兆慶Hung, Chao-ChingChao-ChingHung2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57662隨著CMOS製程技術的進步，超大型積體電路設計在速度上的效能快速的增加，電路的複雜度也越來越高，系統單晶片的實現也不再是夢想了。每個電路模組間的資料通常需要一個經由時脈產生器所產生的時脈來同步化，另外，對某些應用來說，系統也會需要多個相同頻率卻不同相位延遲的時脈，此時，為了確保每個相位間的延遲都相同，多相位時脈產生器的設計就是一個很重要的課題。延遲鎖定迴路與鎖相迴路是兩種非常廣泛的被用來達成系統同步的電路。傳統的延遲鎖定迴路為一階的電路，而鎖相迴路則是高階的電路。相較於高階的電路來說，一階電路具有穩定、容易設計的優點，此外跟鎖相迴路比起來，延遲鎖定迴路的低時脈抖動也是讓它受歡迎的原因之一。 在第一章中，將介紹延遲鎖定迴路的應用與基本理論。延遲鎖定迴路上的參數，如頻寬、抖動效能及鎖定時間將會一一說明。另外有別於之前的理論，新的小訊號模型與分析將會被介紹。 在第二章中，延遲鎖定迴路的設計考量將會被提出。一些常用的相位偵測器、充放電泵及電壓控制延遲單元電路也將分類說明。 在第三章中，我們將會提出一個校正電路，使得延遲鎖定迴路的多相位時脈都具有相同的時脈延遲。利用可變延遲的輸出緩衝器，我們可以用來補償延遲線 上延遲單元間因為製程變異所產生的延遲不匹配。如此一來，我們就可以期望經過輸出緩衝器後的時脈都會有相同的相位延遲。我們所提出的架構是以0.35-微米的互補是金氧半製程製造，電路面積為2.1*1.0平方微米，包含輸入及輸出緩衝電路。 在第四章中，我們介紹量測電路板的製作，量測波形跟電路表現也會被介紹。當輸入時脈頻率為100MHz而操作電壓是3.3V時，量測到的峰值抖動是58ps。 在第五章中，我們將會對這個電路做總結。With the progress of CMOS technique, the speed performance of VLSI system is increasing rapidly. The complexity of circuits becomes higher and higher. Implementation of system on a chip (SOC) is not a dream anymore. The circuits need a global clock which is generated from a clock generator to synchronize the timing among modules. Besides, for some special applications, systems also need clocks which have the same frequency but difference phase. Meanwhile, in order to ensure that the delays among the clocks are the same, the design of multi-phase clock generator is an important issue. DLLs and PLLs are two kinds of circuit which are widely used to synchronize the system. Traditional DLL is a first order circuit and PLL is a higher order circuit. Compared with higher order circuit, first order circuit is simple and stable. Besides, compared with PLL, the property of low jitter performance of DLL is also one reason why it is more popular. In chapter one, applications and basic theory are introduced. The parameters of DLL such as bandwidth, jitter performance, and lock time are also elucidated. Besides, different from former theories, latest small signal model and analysis are elucidated as well. In chapter two, design considerations of DLL are introduced. Some commonly used circuits of the phase detectors, charge pump, and voltage-controlled delay cells are classified. In chapter three, a calibration circuit which can make the multi-phase clocks of DLL have equal delays are presented. With the variable delay output buffer, we can compensate the delay mismatch due to process variations. Therefore, we can expect that these output clocks of the buffers have equal delay. The proposed architecture have been fabricated in a 0.35-um CMOS process. The whole chip area is 2.1*1.0 mm2 including I/O buffers. In chapter four, the fabrication of PCB is introduced. The measured waveform and circuit performance are presented as well. When input frequency is 100MHz and operating voltage is 3.3V, the measured pk-pk jitter is 58ps. In chapter five, we conclude this work.摘要 i Abstract ii Table of Contents iii List of Figures v List of Tables ix Chapter 1 Introductions of the Delay-Locked Loops 1 1.1 Basics of the Delay-Locked Loops 1 1.2 The Applications for DLLs 4 1.2.1 Clock Deskew Buffer 4 1.2.2 Data Links 6 1.2.3 Frequency Multiplier as a Local Oscillator for RF Front End 10 1.3 Theory analysis and model of DLLs 12 1.3.1 Charge Pump DLL model 12 1.3.2 Discrete-time DLL model 14 1.3.3 Jitter Transfer Characteristics 18 Chapter 2 Design Considerations of the Delay-Locked Loop and its Building Blocks 23 2.1 Design considerations of the DLLs 23 2.1.1 Stability Analysis 24 2.1.2 Other considerations of the Delay-Locked Loop 25 2.1.3 Design problems of the Delay-Locked Loop 27 2.2 Building blocks of the DLLs 33 2.2.1 Phase Detector 33 2.2.2 Charge Pump 37 2.2.3 Voltage-Controlled Delay Cell 43 2.2.4 Phase Interpolator 48 Chapter 3 A self-calibrated precisely-equal-delay multiphase DLL-based clock generator 51 3.1 Introduction 51 3.2 Proposed Calibration Algorithm 52 3.3 Monte Carlo Analysis 54 3.4 Circuit Architecture 57 3.5 Circuit description 58 3.5.1 Phase Frequency Detector (PFD) 58 3.5.2 Charge Pump (CP) 59 3.5.3 Voltage Controlled Delay Cell (VCDL) 59 3.5.4 Scaling Linear and Bias Circuits 60 3.5.5 Startup Circuit 61 3.5.6 Lock Detector 62 3.5.7 Phase Comparator and Interpolator 63 3.5.8 Variable Delay Output Buffer 65 3.6 Simulation Result 65 3.6.1 System Behavior Simulation 65 3.6.2 Circuit Level Simulation 67 3.7 Summary 71 Chapter 4 Measurement Setup and Experimental Results 74 4.1 Introduction 74 4.2 Measurement Setup 75 4.3 Print Circuit Board Layout 76 4.4 Experimental Results 81 Chapter 5 Conclusions 90 Bibliography 921522998 bytesapplication/pdfen-US時脈產生器延遲鎖定迴路校正clock generatordelay locked loopcalibrationthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57662/1/ntu-94-R92943063-1.pdf