顧孟愷Ku, Mong-Kai臺灣大學:資訊工程學研究所游超元Yu, Chao-YuanChao-YuanYu2010-06-092018-07-052010-06-092018-07-052009U0001-0808200916080900http://ntur.lib.ntu.edu.tw//handle/246246/185396在這篇論文我們實做了一個IEEE 802.16e 編碼器在FPGA上,我們利用同位元預測與修正的方式來降低在編碼過程中的資料相依性。這個編碼器可以運用在802.16e標準裡的所有碼率和碼長。此篇論文架構能有效的降低硬體複雜度和硬體面積大小並動態的在碼率1/2, 2/3, 3/4, 5/6 和碼長 576 到 2304之間切換. 其結果顯示我們所提出的編碼器架構,無論在生產率和每面積單位生產率上,都勝過一般的的編碼器。In this paper, a FPGA implementation of IEEE 802.16e LDPC encoder is presented. We employ parity bit prediction and correction to break up the data dependency within the encoding process. This encoder implementation can handle sixteen combinations of code rates and code lengths defined in IEEE 802.16e standards. Efficient hardware architecture reduces the complexity and area of encoder that can handle rate: 1/2, 2/3, 3/4, 5/6 and code length: 576 to 2304. Results show that the proposed architecture outperforms conventional works in terms of throughput and throughput/area ratio.口試委員會審定書 i要 iiBSTRACT iiiONTENTS ivhapter 1 Introduction 1.1 The Error Correction Codes 1.2 Low-Density Parity-Check Codes 3.3 Structured LDPC Codes 4.3.1 Quasi-Cyclic (QC) LDPC codes 5.4 LDPC Codes for IEEE Standards 6.4.1 QC-LDPC Codes With Dual-Diagonal Structure 6.4.2 Code description 1.5 Thesis Organization 2hapter 2 Related work 3.1 General Encoding Algorithm for LDPC Codes 3.1.1 RU Algorithm 4.1.2 Encoding Complexity 8.2 Efficient Encoding for Dual-Diagonal LDPC Codes 8.2.1 Characteristics of inverse matrix of T 8.2.2 Linear Encoding 10.3 Arbitrary Bit-generation and Correction Encoding 11.3.1 Encoding Concept 11.3.2 Encoding Scheme 12.3.3 Summary 13hapter 3 Encoder architecture design 14.1 Encoder scheme 14.1.1 Algorithm 14.1.2 Advantage of the algorithm used 17.2 Encoder architecture 17.2.1 Parallel Architecture 18.2.2 Serial Architecture 23.3 Summary 26hapter 4 Implement result 28.1 Hardware Development Environments 28.2 FPGA design flow 29.2.1 C module and simulation 29.2.2 RTL Code Coding 30.2.3 RTL Simulation 30.2.4 FPGA Implementation 30.3 Implementation result 31.4 Compare to related work 36hapter 5 Conclusion and future work 42.1 Conclusion 42.2 Future work 42eference 432319619 bytesapplication/pdfen-US低密度奇偶校驗碼802.16eLDPC高效率IEEE802.16e編碼器設計與實作An Efficient FPGA Implementation of IEEE 802.16e LDPC Encoderthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/185396/1/ntu-98-R95922162-1.pdf