國立臺灣大學電子工程學研究所林宗賢2006-07-262018-07-102006-07-262018-07-102005-07-31http://ntur.lib.ntu.edu.tw//handle/246246/20050本計畫是針對用於OFDM 傳收機中之高效能 CMOS 頻率合成器及感測器介面電路進行研究，而 這個介面電路裡主要包含兩部分，其一為低電壓及 低功率的三角積分類比數位轉換器，因為感測器系 統可能是使用電池做為電源，所以需要低電壓及低 功率以盡量減少功率消耗。為了要無線通訊傳輸， 需要一個頻率合成器，本計劃中提出一10GHz 具有 快速選頻之頻率合成器。Initially, this project was proposed as a sub-project of a 3-year NSC integrated project which aimed to develop a high-performance OFDM transmitter system for medical instrumentation systems. This project is responsible for designing a high-performance frequency synthesizer and key building blocks for the transducer interface module (for ultrasound applications). The integrated project was not recommended by the NSC, and the project became a one-year project. Therefore, we have focused our development effort in two key areas: an agile VCO frequency calibration for a 10-GHz PLL, and a low-power continuous-time dual-mode delta-sigma ADC. In the VCO calibration part, we have proposed a novel technique that can achieve agile frequency calibration. This enables a fast PLL frequency switching, which is important in many wireless communication applications (e.g. frequency hopping systems). This proposed technique is realized in TSMC 0.18um CMOS process and the chip is fully functional. On the second part, we have developed a very low-power low-voltage continuous-time dual-mode delta-sigma ADC. Here, we have proposed an opamp circuit that is suitable for low-power low-voltage applications. We also proposed a sliding quantizer technique which can reduce the number of comparators, and therefore can reduce the power consumption. The whole ADC is also implemented in TSMC 0.18um CMOS process. At the time of writing this report, the chip is under measurement, and initial results suggest functional work. Detail characterization is still underway, and more measurement data will be available later. Our research work has at least generated at least an IEE Electronic Letter paper, a domestic journal paper, and an IEEE international conference paper (A-SSCC).application/pdf1505429 bytesapplication/pdfzh-TW國立臺灣大學電子工程學研究所三角積分類比數位轉換器資料轉換器頻率合成器選頻鎖相迴路相位雜訊delta-sigma ADCdata converterfrequency synthesizerfrequency calibrationPLLphase noisereporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/20050/1/932215E002031.pdf