陳中平臺灣大學：電子工程學研究所郭其偉Kuo, Qi-WeiQi-WeiKuo2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57697一個好的邏輯運算位元最重要的關鍵主要在於以下四點: (1) 運算頻率 (2) 延遲 (3) 消耗功率 (4) 時序可靠性。本篇論文中，我們採用了基板偏壓的方法將延遲-功率乘積作一最佳化。再者，由於製程越來越小，因製程或溫度變異所造成對時序的影響也越來越大。為了克服這個問題，我們在關鍵的時脈點上加入了多個可調延遲的緩衝器。至於加法器架構的選擇方面，我們採用了具有最小面積-延遲乘積的Han-Carlson加法器為基本架構，再用新的方法加以實現。為了供給此高速加法器一高頻訊號，一個鎖相迴路亦包含其中。此外基於量測考量，降頻及自我產生測試訊號的測試電路也是此計劃的一個重點。In this thesis, we present a 32bit Han-Carlson adder that operates at 2.56GHz and is based on TSMC 0.18um bulk CMOS technology. In this work, we optimize the substrate bias of the adder core to achieve a low power-delay product for low power and high speed purposes, and use a post-manufacture tunable clock structure that manipulates the clock at post-fabrication stage to compensate for the process dependent violation to the timing. Simulation results have shown that the substrate-bias optimization results in a 37% of power delay improvement and utilization of tunable delay elements achieve 50 ps of almost linear clock tunability. A phase-locked loop and simple testing circuit also integrate into the chip for timing robustness and measurement purpose. Experiment results show the adder can successfully operate at 2.56GHz working frequency with 1.8V supply voltage.Table of Contents Chapter 1 Introduction 1 1-1 Motivation 1 1-2 Organization 2 Chapter 2 Background of the Adder 4 2-1 Introduction 4 2-2 Conventional adders 4 2-3 Prefix adders 7 2-3.1 Brent-Kung adder 9 2-3.2 Koggy-Stone adder 12 2-3.3 Han-Carlson adder 13 2-4 Summary 16 Chapter 3 Design Considerations and Architecture of the Adder 17 3-1 Introduction 17 3-2 Propagate and generate signal generating stage 17 3-3 Carry-merge tree 18 3-4 Sum signal generating stage 21 3-5 Clock distribution 22 3-5.1 Domino logic timing analysis 23 A. Rising setup analysis 23 B. Falling setup analysis 23 C. Rising hold analysis 24 D. Falling hold analysis 25 3-5.2 Skew-tolerant design 26 3-5.3 Clock tree implementation 31 3-6 Simulation result 32 3-7 Summary 33 Chapter 4 Substrate-Bias Optimized 0.18um 2.5GHz 32-bit 34 Adder with Post-Manufacture Tunable Clock 4-1 Introduction 34 4-2 Substrate bias 34 4-2.1 Threshold voltage and body effect 34 4-2.2 Substrate bias and delay-power product 40 4-3 Post-Manufacture Tunable Clock 43 4-3.1 Process/temperature variation induced clock skew 43 4-3.2 Circuit design and simulation result 44 4-4 Phase-locked loop 45 4-4.1 Review of PLL 45 4-4.2 Phase-frequency detector 48 4-4.3 Charge pump and loop filter 50 4-4.4 Voltage-controlled oscillator 53 4-4.5 Frequency divider 54 4-4.6 Third order PLL 55 4-5 Considerations and procedures of the system 56 4-5.1 PLL 56 4-5.2 Adder 57 4-5.3 Testing Circuitry 57 4-5.3.1 Linear feedback shift register 58 4-5.3.2 Timing issues 59 4-5.3.3 Testing method 60 4-5.4 Simulation result 61 4-6 Experimental result 62 4-7 Summary 64 Chapter 5 Conclusions 65 REFERENCES 661247612 bytesapplication/pdfen-US加法器基板偏壓addersubstrate biasPVT variationthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57697/1/ntu-94-R92943088-1.pdf