Zhu, K.K.ZhuWong, D.F.D.F.WongYAO-WEN CHANG2018-09-102018-09-10200010844309http://www.scopus.com/inward/record.url?eid=2-s2.0-23044523757&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/289941In this paper we present a timing-driven router for symmetrical array-based FPGAs. The routing resources in the FPGAs consist of segments of various lengths. Researchers have shown that the number of segments, instead of wirelength, used by a net is the most critical factor in controlling routing delay in an FPGA. Thus, the traditional measure of routing delay on the basis of geometric distance of a signal is not accurate. To consider wirelength and delay simultaneously, we study a model of timing-driven routing trees, arising from the special properties of FPGA routing architectures. Based on the solutions to the routing-tree problem, we present a routing algorithm that is able to utilize various routing segments with global considerations to meet timing constraints. Experimental results show that our approach is very effective in reducing timing violations. © 2000 ACM.Algorithms; Computer-aided design of VLSI; Design; Experimentation; Field-programmable gate array; Layout; Measurement; Performance; Synthesisjournal article2-s2.0-23044523757WOS:000167918100009