電機資訊學院: 電子工程學研究所指導教授: 林宗賢曾意婷Tseng, Yi-TingYi-TingTseng2017-03-062018-07-102017-03-062018-07-102015http://ntur.lib.ntu.edu.tw//handle/246246/275951本論文包含兩個作品，第一個作品是一個低功耗的連續時間三角積分調變器，主要由一個三階的迴路濾波器、一個被截掉兩位元的六位元量化器所構成；第二個作品是一個具有量化誤差整形效果的八位元量化器所構成。 第一個作品提出了一個把具雜訊整形效果的截除器內嵌於連續逼近暫存量化器的技巧。此位元截除方法可減少數位類比轉換器的數目且可減輕動態匹配電路設計的複雜度，但量化器和截除器之整體反應時間約略是連續逼近暫存量化器需要轉換四個位元的轉換時間。我們用台積電90奈米互補式金氧半製程來實現，經實驗結果得知，本作品在3.5 MHz頻寛下以及110 MHz的取樣頻率下可量到65 dB的訊號雜訊比，調變器的功耗是3.8 mW，整體系統的FoM是350 fJ/Conv.-Step。 第二個作品提出了一個具有量化誤差整形效果的類比數位轉換器，此轉換器貢獻一階雜訊整形效果。此方法有機會在僅使用一個放大器的條件下實現多階量化誤差整形的效果。這個作品在台積電90奈米互補式金氧半製程下實現，在電源供應為1.2 V、取樣頻率為50 MHz的情況下，經量測結果得知，本作品在3.2 MHz頻寛下可量到49.8 dB的訊號雜訊比，調變器的功耗是1.5 mW。Two works are discussed in this thesis. The first work is a low-power continuous-time delta-sigma modulator, which consists of a 3rd-order feed-back and feed-forward combined loop filter structure, a 6-bit quantizer with 2 bits truncated by a truncator and embedded with a noise-shaping mechanism. The second work presents an 8-bit noise-shaped SAR ADC, which improves the resolution of the data converter. A 6-bit, low-power continuous-time delta-sigma modulator (CTDSM) embedded with a noise-shaped and truncated SAR quantizer is proposed in the first work. The bit truncation reduces the number of feedback DAC cells and relaxes the implementation of DEM circuit. The truncation process is embedded in the SAR quantizer which will not degrade the operation frequency of the modulator. Implemented in a 90-nm CMOS process, the measured performance shows a peak SNDR of 65 dB over a signal bandwidth of 3.5 MHz with 110 MHz sampling frequency. This modulator consumes a total power of 3.8 mW, resulting in an FoM of 350 fJ/Conversion-Step. In second work, a low-power 8-bit noise-shaped SAR ADC is discussed. The proposed ADC gives first-order noise-shaping to the modulator, resulting in an 8-bit 1st-order delta-sigma modulator. This method has the opportunity to extend to higher-order noise-shaping using only one operational amplifier with the help of finite impulse response (FIR) filter. This modulator was realized in a 90-nm CMOS process. Under a power supply of 1.2 V and a sampling frequency of 50 MHz, the measured performance shows a peak SNR and SNDR of 56 dB and 49.8 dB, respectively, over a signal bandwidth of 3.2 MHz. The modulator consumes a total power of 1.5 mW.論文使用權限: 不同意授權雜訊整形連續逼近暫存量化器noise-shapingSAR ADCthesis