Chen, Tung-ChienTung-ChienChenTsai, Chuan-YungChuan-YungTsaiHuang, Yu-WenYu-WenHuangLIANG-GEE CHEN2009-02-252018-07-062009-02-252018-07-06200710518215http://ntur.lib.ntu.edu.tw//handle/246246/141471https://www.scopus.com/inward/record.uri?eid=2-s2.0-33847738637&doi=10.1109%2fTCSVT.2006.887130&partnerID=40&md5=982c0981b62c84c496f54a183d75a089Due to the multiple reference frame motion estimation (MRF-ME), an H.264/AVC encoder requires ultrahigh memory bandwidth. Conventional multiple reference frames single current macroblock (MRSC) scheme only considers the data reuse within one frame, and requires on-chip memory size and off-chip memory bandwidth in proportional to the reference frame number. In this paper, a single reference frame multiple current macroblocks (SRMC) scheme is presented to further exploit the data reuse at frame level. With frame-level rescheduling of the motion estimation ME procedures in different reference frames, one loaded search window can be utilized by multiple current MBs in different original frames. The demanded on-chip memory size and off-chip memory bandwidth for MRF-ME can thus be reduced to those supporting only one reference frame. Moreover, based on SRMC scheme, an architecture prototype with two-stage mode decision flow is proposed. For HDTV specifications, 62.21 KB (74.8%) of SRAM and 364.3 MB/s (62.6%) of system bandwidth are saved in comparison with the MRSC scheme. © 2007 IEEE.application/pdf708077 bytesapplication/pdfen-USISO/IEC 14496-10 AVC; ITU-T Rec. H.264; JVT; Motion estimation; Multiple reference frame; VLSI architectureDecision flow; Multiple reference frame; VLSI architecture; Bandwidth; Decision theory; Image coding; Search engines; Storage allocation (computer); Motion estimationjournal article10.1109/TCSVT.2006.8871302-s2.0-33847738637WOS:000244117300010http://ntur.lib.ntu.edu.tw/bitstream/246246/141471/1/59.pdf