Liu, Min-HsinMin-HsinLiuCheng, Ding-WeiDing-WeiChengLi, James Chien-MoJames Chien-MoLiNigh, ChrisChrisNighGoh, Szu HuatSzu HuatGohChern, MasonMasonChernHsieh, Bing-HanBing-HanHsiehKundu, SubhadipSubhadipKundu2026-01-122026-01-122025-09-20[9798331570415]10893539https://www.scopus.com/record/display.uri?eid=2-s2.0-105024557169&origin=resultslisthttps://scholars.lib.ntu.edu.tw/handle/123456789/735237At-speed logic scan tests are an important tool to ensure desired quality in mobile chips. During initial test pattern bring-up, tests that exhibit an unexpectedly high Vmin pose a risk of over-testing and production yield loss. This is particularly problematic if the Vmin of the test is significantly higher than that of the functional system workloads. In such situations, the at-speed logic scan test is debugged to find and resolve the source of the high Vmin. This paper describes an example case study of Vmin debug, in which a series of experiments are performed to identify the root cause as individual test patterns that capture the responses of unconstrained paths. We propose pre-silicon and post-silicon methods to improve Vmin by preventing problematic patterns and reducing the debug effort during test bring-up. Our methods have been verified on ATE to effectively improve Vmin by 28.83mV to 39.33mV with 0% to 0.5% pattern count inflation.falseDelay TestDiagnosisUnconstrained PathVmin[SDGs]SDG13conference paper10.1109/itc58126.2025.000262-s2.0-105024557169