Chuang, C.-N.C.-N.ChuangSHEN-IUAN LIU2020-06-112020-06-11200915497747https://scholars.lib.ntu.edu.tw/handle/123456789/499882https://www.scopus.com/inward/record.uri?eid=2-s2.0-70549111584&doi=10.1109%2fTCSII.2009.2032477&partnerID=40&md5=4a40c8ac734b27814715f9b9787965d5A 20-MHz to 3-GHz wide-range multiphase delay-locked loop (DLL) has been realized in 90-nm CMOS technology. The proposed delay cell extends the operation frequency range. A scaling circuit is adopted to lower the large delay gain when the frequency of the input clock is low. The core area of this DLL is 0.005 mm2. The measured power consumption values are 0.4 and 3.6 mW for input clocks of 20 MHz and 3 GHz, respectively. The measured peak-to-peak and root-mean-square jitters are 2.3 and 16 ps at 3 GHz, respectively. © 2009 IEEE.Delay cell; Delay-locked loop (DLL); Multiphase; Wide range[SDGs]SDG7Clocks; Consumption values; Delay cell; Delay-locked loops; Large delays; Multiphase; Operation frequency ranges; Root Mean Square; Wide range; Delay lock loopsjournal article10.1109/TCSII.2009.20324772-s2.0-70549111584