郭斯彥臺灣大學：電子工程學研究所吳則霖WU, TES-LINTES-LINWU2007-11-272018-07-102007-11-272018-07-102006http://ntur.lib.ntu.edu.tw//handle/246246/57491隨著SOC複雜度的快速成長，驗證所需要的模擬時間也就越來越長，使得效率大打折扣。也因此，傳統的硬體驗證方式就越來越趕不上腳步。要如何節省驗證的時間是目前非常重要的一個課題。 為了解決上述的問題，本論文提出了一套Consumer Electronics Advanced Technology Attachment (CE-ATA)的匯流排功能性模組(Bus Functional Model)。並且利用Verilog行為語法以及驗證語言擴增(Verification Language Extension)工具的輔助來實作。 此外，本論文還利用了transaction based, assertion based, coverage based來建構出一個驗證環境，以求能夠對CE-ATA的晶片設計者提供更大的幫助。As the rapid growth of the complication of SOC, the simulation time spent on verification is getting longer and longer, which results in low efficiency. That is why the traditional method of verification started to be left behind. How to save the time on verification is a very important issue nowadays. To solve the above problem, this thesis represents a set of Bus Functional Model (BFM) of Consumer Electronics ATA (CE-ATA), and uses tools such as Verilog behavior language and verification language extension. Besides, this thesis also uses several methodologies, transaction based, assertion based, coverage based, to build a verification environment, in order to offer greater help for the chip designer of CE-ATA.致謝 2 摘要 3 Abstract 4 List of Figure 7 List of Table 8 Chapter 1 Introduction 11 1.1 Bus Functional Models 11 1.2 Concepts of Verification 12 Chapter 2 Overview of CE-ATA System 13 2.1 General Overview 13 2.1.1 Parallel ATA Interface 13 2.1.2 Serial ATA Interface 14 2.1.3 Consumer Electronics ATA Interface 15 2.2 CE-ATA Architecture 17 2.2.1 MMC Command 17 2.2.1.1 RW_MULTIPLE_REGISTER (CMD60) 18 2.2.1.2 RW_MULTIPLE_BLOCK (CMD61) 19 2.2.2 Reduced ATA Command Set 20 2.2.2.1 ATA Command Emulation 20 2.2.2.2 Reduced ATA Command Set 22 2.2.3 Command Executing 25 2.2.3.1 Communication signals 25 2.2.3.2 Transfer Mode: Interrupts Enabled, Polling 30 Chapter 3 Implementation of CE-ATA 35 3.1 TestWizard 35 3.1.1 Record Function 36 3.1.2 List Function 40 3.2 CE-ATA BFM Implementation 43 3.2.1 ATA Layer 44 3.2.2 MMC Command Layer 54 3.2.3 MMC Data Layer 59 3.3 Error Insertion 63 Chapter 4 CE-ATA Verification Environment 65 4.1 Testbench 65 4.2 Checklist 69 4.3 Experimental Results 71 Chapter 5 Conclusion and Future Works 72 5.1 Conclusion 72 5.2 Future Works 72 References 731150471 bytesapplication/pdfen-US配接器消費性電子ATACEthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57491/1/ntu-95-R93943110-1.pdf