臺灣大學: 電子工程學研究所黃鐘揚林暐勛Lin, Wei-HsunWei-HsunLin2013-04-102018-07-102013-04-102018-07-102012http://ntur.lib.ntu.edu.tw//handle/246246/256707在超大型積體電路設計階段中，功能修正已變成一個不可或缺的過程。傳統上，功能修正藉由許多組合電路的技術而達成，然而其並沒有考慮暫存器對於功能改變的彈性，因此，這些組合電路的技術並沒有辦法直接使用在有不匹配暫存器的循序電路上。在這篇論文中，我們提出了一個修正循序電路的方法，其使用了必然性模型檢測技術來檢驗舊設計電路與新規格電路的可修正性。此外，我們利用了內插邏輯技術來產生修正函數，並藉由找尋較好的基底變數，加速了整體修正過程。實驗結果顯示我們所提出的方法可以有效率地決定一個給定的信號是否可以將電路修正，並且能有效地產生夠小的修正函數。最後，我們的方法提供了組合性修正另一條路，而且可於大部分的實驗中產生較小的修正函數。Functional rectification has been an indispensable process in late VLSI design stages. Traditionally, functional rectification is achieved by various techniques on combinational circuits. It does not explore the flexibility of functional changes across the register boundary. As a result, these combinational rectification techniques cannot be applied directly to sequential circuits with unmatched registers. In this thesis, we propose a sequential rectification approach, which utilizes the liveness model checking techniques to facilitate checking of the sequential rectifiability between old implementation and golden specification. In addition, we apply the interpolation technique to construct the rectification function (i.e. the patch). By identifying better supports for the patch generation, we demonstrate that the whole procedure can be accelerated. Experimental results show that our method can efficiently determine whether a given signal is a rectification signal and find the patch circuits effectively. In the end, our method can provide an alternative way to the combinational rectification and it generates smaller in most of cases.140 bytestext/htmlen-US功能修正必然性性質模型檢測Functional RectificationLiveness PropertyModel Checkingthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/256707/1/index.html