Lai Y.-PChang H.-HTAI-CHENG LEE2023-06-092023-06-092022https://www.scopus.com/inward/record.uri?eid=2-s2.0-85130468030&doi=10.1109%2fVLSI-DAT54769.2022.9768072&partnerID=40&md5=4c7729d7787cb28fc2147f0bb7bbb7cchttps://scholars.lib.ntu.edu.tw/handle/123456789/632324A 20 Hz 2nd-order discrete-time incremental sigma-delta modulator with 1-bit quantizer is proposed by utilizing zero-crossing-based integrator with asynchronous clock system. This prototype fabricated in a UMC 28 nm HPC Plus CMOS technology, achieving 11.5-bit ENOB at 40 S/s conversion rate with an over-sampling ratio (OSR) of 256, and yielded a Schreier FoM of 165.5 dB. The modulator occupies an active area smaller than 0.105 mm2 and consumes 141.1 nW. © 2022 IEEE.asynchronous; delta-sigma modulator; high resolution; Incremental delta-sigma data converter; low power; zero-crossing-based circuitsDelta sigma modulation; Low power electronics; Modulators; Asynchronoi; Data converter; Delta-sigma; Delta-sigma converters; Discrete time; High resolution; Incremental delta-sigma data converter; Low Power; Zero-crossing-based circuit; Zero-crossings; Timing circuitsconference paper10.1109/VLSI-DAT54769.2022.97680722-s2.0-85130468030