闕志達臺灣大學：電機工程學研究所蔡佩芸Tsai, Pei-YunPei-YunTsai2007-11-262018-07-062007-11-262018-07-062005http://ntur.lib.ntu.edu.tw//handle/246246/53310多載波調變(Multi-Carrier Modulation，如正交分頻調變 Orthogonal Frequency Division Multiplexing)技術，相對於單一載波調變，有助於達成寬頻傳輸及提昇頻譜效能，並可維持合理系統複雜度。多載波調變目前已廣見於各式系統中，而第三代行動通訊系統的兩大主流規格，W-CDMA與CDMA3X，也可見到多載波調變的研究與採行。在多載波調變方式之推廣研究中，多載波碼域多工(MC-CDMA) 系統因結合直接序列展頻多工與正交分頻調變方式，兼具兩種系統特點，故已被視為具有相當潛力之下世代多工傳輸技術。下世代的無線網際網路系統如同現有的有線寬頻網際網路系統(xDSL或cable modem)一般，可預期下行(downlink)的流量將遠大於上行(uplink)的流量。因此所設計的系統之目的在於利用一可大幅度增加傳輸速度的多載波碼域多工通訊方式來提供下世代的無線網際網路下行系統新的解決方案。 我們所提出的多載波碼域多工系統目標在提高現有3G (W-CDMA)都會區蜂巢式通訊系統之下行傳輸率，因此所提出的系統使用相同的射頻頻段，享有相同的頻寬。並根據3GPP所提供都會區的通道資料以及應支援的行動速度(mobility)，進而訂定出系統規格。同時，針對多載波系統所必須克服的同步(synchronization)問題，提出最小加權方差(weighted least squares, WLS)的演算法來聯合估測(joint estimation)載波頻率誤差與取樣時脈誤差，以減少因同步所招致的子載波間干擾(inter-carrier interference)與多使用者干擾(multiple access interference)，為了解決高速移動下的通道估測問題，也提出了頻域的通道內插器，而見諸於整體系統的效能，也驗證了所提出的演算法之有效性。 最後，將所設計的系統進行晶片實作驗證，為了達到手機端低功率與低複雜度的要求，我們提出架構上的改善包括: 全客戶設計的位元反轉機制，可節省50%的記憶體; 新穎的通道內插方式也可除去時域演算法所需要額外的快速傅立葉轉換之硬體與大量的記憶體; 利用座標軸旋轉(CORDIC)演算法來設計低複雜度卻有優異表現的硬體等化架構; 也採用了閘控時脈(gated clock)，單阜靜態存取記憶體(single-port SRAM)，低功率延遲暫存器，以及座標軸旋轉演算法來運算複數之相位以節省面積與功耗。經由驗證，本晶片在5.76 MHz的操作頻率下， 1.1V的工作電壓，只消耗9.9mW，最快的傳輸速率可到21.7 Mbps，而其優異之功能表現為下一世代的行動通信系統提出一新的解決方案。In this thesis, design and implementation of an MC-CDMA transceiver for next-generation mobile communication systems are presented. The proposed system uses the same RF frequency and signal bandwidth as those of the 3G W-CDMA standards, for its major goal is to increase the downlink data rate of the current cellular communication system in urban areas. The system specifications and parameters are chosen according to the channel models and the highest mobility specified by 3GPP. Since multi-carrier systems are well known to be vulnerable to synchronization errors, to decrease ICI and MAI resulting from carrier frequency offset (CFO) and sampling clock offset (SCO), we propose to jointly estimate the residual CFO and SCO by a weighted least squares algorithm. Besides, in order to provide accurate channel estimates in fast-fading channels, a new frequency-domain channel interpolator based on pilot subcarriers is proposed to track channel variation. The entire MC-CDMA receiver is integrated and implemented in 0.18 $mu$m CMOS technology. To achieve the target of low power and small area of mobile units, we have custom-designed bit-reversal architecture with reduced SRAM requirements. A novel channel interpolation algorithm is incorporated with much less hardware complexity but more improved accuracy. In addition, a CORDIC-based TORC equalizer architecture is implemented to save power and area. Experimental results of the designed baseband receiver IC demonstrate its superior system performance up to 21.7 Mbps uncoded data rate. When running at 5.76 MHz, its power consumption is as low as 9.9 mW from a supply voltage of 1.1V.1 Introduction 1.1 Current Status of B3G . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Motivation of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Organization of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Principle of OFDM and MC-CDMA 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Orthogonal Frequency-Division Multiplexing . . . . . . . . . . . . . . . . 11 2.3 Multicarrier Modulation and CDMA . . . . . . . . . . . . . . . . . . . . 14 3 Baseband Channel Model 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 Transmitter Impairment . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.1 DAC Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.2 Power Amplifier Non-linearity . . . . . . . . . . . . . . . . . . . . 23 3.3 Radio Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.1 Multipath Fading Channel . . . . . . . . . . . . . . . . . . . . . . 25 3.3.2 Additive White Gaussian Noise . . . . . . . . . . . . . . . . . . . 33 3.4 Receiver Impairments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4.1 Carrier Frequency Offset (CFO) . . . . . . . . . . . . . . . . . . . 34 3.4.2 Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4.3 I/Q Imbalance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4.4 DC Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.4.5 Sampling Clock O set (SCO) . . . . . . . . . . . . . . . . . . . . 37 4 A New Joint Estimation Algorithm for CFO and SCO in OFDM Systems 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2 Synchronization in OFDM systems . . . . . . . . . . . . . . . . . . . . . 43 4.2.1 Definition of Synchronization Errors . . . . . . . . . . . . . . . . 43 4.2.2 Effects of Synchronization Errors . . . . . . . . . . . . . . . . . . 43 4.2.3 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . 49 4.3 Joint Estimation Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3.2 Impact of Both CFO and SCO . . . . . . . . . . . . . . . . . . . 53 4.3.3 Prior Joint Estimation Algorithms . . . . . . . . . . . . . . . . . 55 4.3.4 Proposed Joint WLS Estimator . . . . . . . . . . . . . . . . . . . 56 4.3.5 Performance Simulation . . . . . . . . . . . . . . . . . . . . . . . 64 5 Novel Frequency-Domain Channel Interpolation in OFDM Systems 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.2 Pilot Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.3 Channel Estimation By Block-Type Pilot Symbols . . . . . . . . . . . . . 75 5.3.1 MMSE Channel Estimator . . . . . . . . . . . . . . . . . . . . . . 79 5.3.2 LS Channel Estimator . . . . . . . . . . . . . . . . . . . . . . . . 79 5.4 Channel Estimation By Comb-Type Pilot Subcarriers . . . . . . . . . . . 80 5.4.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.4.2 Time-Domain Windowing and Frequency-Domain Interpolation . 81 5.4.3 Conventional Polynomial-Based Channel Interpolator . . . . . . . 83 5.4.4 Proposed Channel Interpolator . . . . . . . . . . . . . . . . . . . 86 5.4.5 Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.4.6 Performance Simulation . . . . . . . . . . . . . . . . . . . . . . . 95 5.4.7 Complexity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6 MC-CDMA System Design 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2 System Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3 Transmitter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3.1 Convolutional Coding . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.2 Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.3.3 Constellation Mapping . . . . . . . . . . . . . . . . . . . . . . . . 112 6.3.4 Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.3.5 Pilot Subcarrier Insertion . . . . . . . . . . . . . . . . . . . . . . 117 6.3.6 Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.3.7 Training Symbol Insertion . . . . . . . . . . . . . . . . . . . . . . 118 6.3.8 OFDM Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.4 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.4.1 Coarse Symbol Timing Detection . . . . . . . . . . . . . . . . . . 122 6.4.2 Fractional Carrier Frequency Offset Estimation . . . . . . . . . . 124 6.4.3 Integer Carrier Frequency Offset Acquisition . . . . . . . . . . . . 125 6.4.4 Fine Symbol Timing Detection . . . . . . . . . . . . . . . . . . . 125 6.4.5 Joint WLS Estimation . . . . . . . . . . . . . . . . . . . . . . . . 126 6.4.6 Channel Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.4.7 Combining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6.4.8 De-Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.4.9 Convolutional Decoding . . . . . . . . . . . . . . . . . . . . . . . 139 6.5 System Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 7 Hardware Implementation 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7.2 Fixed-Point Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 7.3 Low-Power and Low-Complexity Architecture and Circuit Design . . . . 149 7.3.1 Coarse Symbol Timing Detection . . . . . . . . . . . . . . . . . . 149 7.3.2 Fractional CFO Estimation . . . . . . . . . . . . . . . . . . . . . 149 7.3.3 FFT Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 7.3.4 Integer CFO Acquisition . . . . . . . . . . . . . . . . . . . . . . . 153 7.3.5 Fine Symbol Timing Detection . . . . . . . . . . . . . . . . . . . 155 7.3.6 Joint WLS Estimation . . . . . . . . . . . . . . . . . . . . . . . . 156 7.3.7 Recovery Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 7.3.8 Channel Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . 159 7.3.9 Combining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 7.3.10 Resource Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 7.3.11 Gated Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.3.12 Saving in Complexity and Power . . . . . . . . . . . . . . . . . . 164 7.4 Design for Testibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 7.4.1 SRAM Build-In-Self-Test . . . . . . . . . . . . . . . . . . . . . . . 168 7.4.2 Scan Chain Insertion . . . . . . . . . . . . . . . . . . . . . . . . . 168 7.4.3 Ad-Hoc Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 7.5 Physical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.6 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 7.7 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 7.7.1 Measurement Environment . . . . . . . . . . . . . . . . . . . . . . 174 7.7.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 175 7.7.3 System Performance . . . . . . . . . . . . . . . . . . . . . . . . . 177 8 MIMO Extension 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 8.2 Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 8.2.1 MIMO System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 8.2.2 MIMO-OFDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 8.3 MC-CDMA with STBC . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 8.3.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 8.3.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 8.4 Hardware Modification From SISO To MIMO . . . . . . . . . . . . . . . 194 9 Conclusion 197 A Mean of Phase Error 199 B Variance of Phase Error 201 C Covariance of Phase Error 2054195829 bytesapplication/pdfen-US多載波碼域多工基頻收發機同步通道估測multi-carrierCDMAbaseband transceiversynchronizationchannel estimationthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/53310/1/ntu-94-D89921001-1.pdf