Yao Y.-SHuang C.-CSHEN-IUAN LIU2021-09-022021-09-02202115497747https://www.scopus.com/inward/record.uri?eid=2-s2.0-85098759299&doi=10.1109%2fTCSII.2020.3045180&partnerID=40&md5=8c133b943a46bc4042709142a6489369https://scholars.lib.ntu.edu.tw/handle/123456789/581134To improve the jitter tolerance (JTOL) of a clock and data recovery (CDR) circuit, a background loop gain controller (BLGC) is presented. This CDR circuit is realized in a 40nm CMOS process. Its active area is 0.0324mm2 and the power consumption is 12.67mW from a 1 V supply. For 1-Gb/s and 3-Gb/s PRBS of 215-1 and the bit error rate < 10-12 , the measured root-mean-square jitter of the retimed data are 12.3ps and 7.74ps, respectively. By using the proposed BLGC, the minimum high-frequency JTOL at 3-Gb/s is improved to 0.68 UIpp. ? 2004-2012 IEEE.background loop gain controller; clock and data recovery; jitter; Jitter toleranceBit error rate; Gain control; Jitter; Timing circuits; 40nm cmos; Active area; Clock and data recovery; High frequency HF; Jitter tolerance; Loop gains; Root mean square jitter; Clock and data recovery circuits (CDR circuits)journal article10.1109/TCSII.2020.30451802-s2.0-85098759299