臺灣大學: 電子工程學研究所郭正邦吳威宏Wu, Wei-HongWei-HongWu2013-04-102018-07-102013-04-102018-07-102010http://ntur.lib.ntu.edu.tw//handle/246246/256972近年來隨著積體電路製程的縮小化,必須將更多元件集結在單一晶片上,因此電路複雜度也隨之增加,同時要考慮到速度及功率問題成為一大課題。 這篇論文主要探討一個加快電路速度的有效方法,並組成更高階的電路,第一章會先介紹CMOS超大型積體電路原由、功率消耗及模擬軟體介紹。 第二章則正式介紹實驗模擬的電路,本論文以16-bit Wallace tree 乘法器為測量電路,操作電壓設定為0.5V,並加入Pipeline Latch做成Pipeline Latch結構,透過新思(Synopsys)公司所開發的Primetime工具分析結果,與原本未加的電路比較可增加將近257%的操作頻率,由於電路中最終加法器(Final Adder)部分仍有過大的延遲,因此在這加入1V的操作電壓,與未加1V的電路比較可增大95%的操作頻率。 第三章則是利用16-bit乘法器組成更高階的乘法器電路,與直接用Wallace結構去組成比較後,速度與消耗功率並未變好,但設計複雜度降低許多,可以方便擴大更高階的電路,另外提供改善此乘法器速度的方法,將最終加法器(Final Adder)部分加入Pipeline Latch,可使無論擴充到多高bit的乘法器最大操作頻率保持一致。 第四章為結論和未來研究方向。The integrate-circuit technology scale down recently, more functionality can be combined into a single chip. So circuit complexity thereupon increases, performance and power consumption will be considered. The thesis describe a ways to increase speed of a circuit, and make up the high-level circuit. Chapter 1 introduce CMOS very large scale integrated circuits reason, power consumption and simulation software . Chapter 2 introduces a 16-bit Wallace tree multiplier circuit with VDD = 0.5V. Latch technology insert the multiplier become pipeline structure. Using Synopsys Primetime EDA tool analyses result, We can get the 257% increase operation frequency. Because of the final adder is bigger delay than other path of the multiplier circuit, so we can get the 95% increase operation frequency by change the VDD = 1V. Chapter 3 introduces a high-level multiplier circuit consists of 16-bit multiplier circuits, compare with high-level Wallace multiplier, performance and power consumption have not been improved, but is easily scalable to higher bit precision by duplicating sub-multiplier and adding an additional levels of reduction, allows for short design time. We have a way to increase speed by insert pipeline latch into final adder of the high-level multiplier.140 bytestext/htmlen-US高階合成低電壓低功率PipelineLatchMultiplier使用高階合成達成低電壓低功率互補式金氧半技術Low-Voltage Low-Power CMOS Multiplier Design Using Pipeline Latch High-Level Synthesis Approachthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/256972/-1/ntu-99-R97943095-1.pdf