李致毅臺灣大學：電子工程學研究所劉明忠Liu, Ming-ChungMing-ChungLiu2007-11-272018-07-102007-11-272018-07-102007http://ntur.lib.ntu.edu.tw//handle/246246/57516我們提出一個採用注入鎖定技術的二十億位元每秒突發式時脈資料回復電路，其可在低功率消耗之下達到高速操作。此電路利用產生與資料速率相同的頻率成分，達到鎖定兩級電感電容震盪器的效果。另外使用一個參考鎖相迴路達到頻率監測的效果，使壓控震盪器的自振頻率與資料速率有良好的匹配。此時脈資料回復電路採用九十奈米互補金氧半電晶體製程製作，其可以達到，在使用231-1偽隨機二進制序列連續模式操作，以及突發模式的操作之下，達到小於10-9之位元錯誤率。晶片面積為0.8 mm X 1.2 mm，且在1.5 V電壓操作下消耗 175 mW。A 20-Gb/s clock and data recovery circuit incorporates injection-locking technique to achieve high-speed operation with low power dissipation. The circuit creates spectral line at the frequency of data rate and injection-locks two cascaded LC oscillators. A frequency-monitoring mechanism is employed to ensure a close matching between the VCO natural frequency and data rate. Fabricated in 90-nm CMOS technology, this circuit achieves a bit error rate of less than 10-9 in both continuous (PRBS of 231-1) and burst modes while consuming 175 mW from a 1.5-V supply.口試委員會審定書 i 摘要 v Abstract vii Chapter 1 Introduction 1 1.1 Why Clock and Data Recovery 1 1.2 Continuous Mode and Burst Mode 2 1.3 Thesis Organization 5 Chapter 2 Architecture and Consideration 7 2.1 Existing solution 7 2.2 Proposed Architecture 9 Chapter 3 Design of High-speed Burst-mode Clock and Data Recovery Circuit 15 3.1 VCO and Clock Buffer 15 3.2 Variable Delay Buffer, XOR Gate, and Flipflop 17 3.3 Unity Gain Buffer 19 3.4 Reference PLL 22 Chapter 4 Consideration of Injection-Locking and Finite Frequency Offset 33 4.1 Injection Locking in Oscillator 33 4.2 Finite Frequency Offset 38 Chapter 5 Measurement Result 43 5.1 Layout and Testing Setup 43 5.2 Testing Result of Reference PLL 45 5.3 Testing Result of CDR 46 Chapter 6 Conclusion 53 Biography 552677777 bytesapplication/pdfen-US時脈資料回復電路突發式注入鎖定Clock and Data RecoveryBurst-ModeInjection-lockingthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57516/1/ntu-96-R94943013-1.pdf