A 60 GHz CMOS power amplifier with modified pre-distortion linearizer

Hsu, Y.-C.Y.-C.HsuKao, K.-Y.K.-Y.KaoKao, J.-C.J.-C.KaoTsai, T.-C.T.-C.TsaiKUN-YOU LIN2018-09-102018-09-102013http://www.scopus.com/inward/record.url?eid=2-s2.0-84893325237&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/379831This paper proposes a new pre-distortion linearizer for CMOS power amplifier (PA) to improve the performance of the output 1-dB compression power and power added efficiency at 1-dB compression power. By adopting the proposed pre-distortion linearizer, a 60 GHz cascode PA with 13.7-dBm 1-dB compression power (P1dB) and 14.3% power added efficiency (PAE) at P 1dB is demonstrated. The chip size is 0.55 × 0.45 mm 2 including all testing pads.60 GHzCMOSPower amplifiersPre-distortion linearizer[SDGs]SDG7A 60 GHz CMOS power amplifier with modified pre-distortion linearizerconference paper10.1109/MWSYM.2013.66973592-s2.0-84893325237