Lin, Hsin ChengHsin ChengLinChiu, Kuan YingKuan YingChiuYao, Ching WangChing WangYaoChou, TaoTaoChouChung, Tsai YuTsai YuChungCHEE-WEE LIU2023-08-212023-08-212023-01-019798350334166https://scholars.lib.ntu.edu.tw/handle/123456789/634632RF performance of stacked nanosheet (NS) and stacked nanowire (NW) nFETs is studied and optimized by validated TCAD simulation considering the double-sided (DS) gate contact and contact over active-gate (COAG) transistor array layouts. The back-end-of-line (BEOL) up to M3 level is included. As compared to stacked NSs, stacked NWs have smaller effective width (Weff) and smaller channel cross section, leading to smaller intrinsic capacitance (Cox) and smaller output conductance (gd) under similar transconductance (gm) and similar parasitic capacitance (Cpar). Thus, better RF performance of stacked NWs can be achieved. In this work, the vertically stacked channel numbers (floor#) of stacked NSs/NWs are optimized under different lateral-stack numbers of transistor arrays considering DS gate contact and COAG layouts.conference paper10.1109/VLSI-TSA/VLSI-DAT57221.2023.101341102-s2.0-85163026867https://api.elsevier.com/content/abstract/scopus_id/85163026867