Circuit Partition and Reordering Technique for Low Power IP

Kun-lin TsaiShanq-jang RuanChun-ming HuangEdwin NaroskaFEI-PEI LAI2018-09-102018-09-102004-04http://scholars.lib.ntu.edu.tw/handle/123456789/310845Circuit Partition and Reordering Technique for Low Power IPjournal article2-s2.0-2342579571WOS:000220778100025