臺灣大學: 電子工程學研究所汪重光王照勳Wang, Chao-ShiunChao-ShiunWang2013-04-102018-07-102013-04-102018-07-102010http://ntur.lib.ntu.edu.tw//handle/246246/256841隨著高畫質影音與高速儲存系統的普及,使用者對於高速無線資料傳輸的需求越來越高,傳統的通訊系統頻寬以及傳輸方式無法即時的傳輸這麼大的資料,因此具有寬頻高速的毫米波無線資料傳輸方式日受矚目。在傳統的毫米波電路設計中,多是採用特性較好的III/V族元件製作,但是隨著CMOS製程不斷的進步提升,使得今日的CMOS元件也有可能用來設計毫米波電路,加上CMOS製程具有低成本、高整合性的優點,因此使用CMOS 來設計毫米波無線傳輸系統將有可能將射頻電路與基頻訊號處理電路整合成一個便宜的系統晶片。不過,使用短波長的毫米波來傳遞資料遇到的最大的問題是訊號在空氣中傳播所造成的衰減,這將使得整個無線通訊系統需要較高的訊號雜訊比來達到高速傳輸的目的。因此所設計的電路除了需克服CMOS元件先天上的限制外,在系統、架構與電路設計上都需要有特別考慮來提升整體系統的表現。 本論文主要將探討使用不同CMOS先進製程(65nm、90nm與130nm)來設計毫米波電路的技巧與方法。研究目標在於開發高速、低功耗與高整合度的無線通訊接收機關鍵電路以應用於毫米波頻帶中的60GHz系統。在論文中的電路設計上,首先將探討先進製程元件的特性與極限,並針對低雜訊與低功耗的毫米波系統需求,設計使用增益放大、電流共享與雜訊消除技術的低雜訊放大器與接收機的關鍵電路。在子系統的整合開發上,將完成一個使用主動式旋相器的高整合性雙天線相位陣列接收機,以及一個使用注入式鎖定技術、具有低複雜度與高可靠性的高速資料CPFSK/MSK解調變器。 論文中所提出的雙天線相位陣列接收機射頻前端電路是採用130nm的RF CMOS製程來實現。為了得到較好的共模雜訊抑制,此一階收機前端電路採用全差動式電路設計。提出利用增益提升、電流共享與雜訊消除技術的低雜訊放大器電路以降低來自雜訊、增益、可靠度、穩定度與線性的設計挑戰,使用次諧波雙閘極混波器的電路架構來降低因為本地振盪器三次諧波所造成干擾的問題,而本地振盪器的相位旋轉則是採用主動式全通濾波器架構來實現。最後經由下線量測驗證,所設計的晶片可以提供34.5dB的增益以及提升了4.5dB的訊號雜訊比,而整體電路在1.2伏特的操作電壓下消耗了93毫瓦的功率。 使用注入式鎖定技術、具有低複雜度與高可靠性的高速資料FSK/MSK解調變器也是採用130nm的RF CMOS製程來實現。與傳統被動元件的電感與電容式解調變器相比,使用注入式鎖定技術的FSK/MSK解調變器可以校正受製程、偏壓、溫度變化影響的頻率對相位轉換。根據量測結果,所提出的解調變器最快可還原的調變資料是調變指數為0.5的2.5Gbps MSK調變訊號,此時的最小輸入訊號大小是-12dBm。整體的晶片在1.2伏特的操作電壓下消耗了20毫瓦的功率,其中只有6毫瓦是使用在解調變電路的部分。Recently, the interest in millimeter-wave radio links has increased. This is caused by application that needs wireless radio links with high data rates. By using today''s advanced CMOS technologies, it allows relatively cheap implementations for such radio links. The short wavelength of the millimeter-wave signals suffer from the serious attenuation in the atmosphere and multi-path channels, which hinders the wireless communication from achieving high SNR performance required by high throughput system specifications. This puts special requirements on system design, architecture and circuits. This dissertation investigated circuit design techniques operating at the millimeter-wave frequency using advanced 65nm, 90nm and 130nm CMOS technologies. The goal of the research is to realize high-speed, low-power, and compact integrated wireless communication key blocks operating at 60 GHz frequency. The various current-reused and noise cancelling LNA circuits and receiver building blocks toward the realization of the low power and low noise millimeter-wave systems are presented in this dissertation. On the system side, a fully integrated dual-antenna phased-array RF front-end receiver including the active phase shifter has been demonstrated. A less complex analog FSK demodulator using an injection-locked technique to achieve a gigabit data rate without suffering from process variation is also exhibited. The proposed dual-antenna phased-array RF front-end receiver was designed and fabricated in a 0.13um RF CMOS process. In order to obtain good common-mode noise rejection, the receiver front-end employs fully differential architecture. The proposed gm-boosted current-reuse LNA circuit mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down conversion mixer alleviates the problem of the third harmonic of the LO as well. An active all-pass filter is employed to adjust the phase shift of each LO signal. This architecture exhibits a measured SNR improvement of 4.5 dB with an overall measured gain of 34.5 dB. Overall chip power consumption is 93mW. The proposed injection-locked high data-rate FSK/MSK demodulator is fabricated in a 0.13um CMOS RF technology. Compared with the conventional LC tank discriminator, the injection-locked oscillator provides a process insensitive frequency-to-phase transformation for analog non-coherent FSK/MSK demodulation. The measured demodulation input sensitivity is -12dBm at BER less than 10^-9 for uncoded 2.5Gbps 2^31-1 PRBS data with 0.5 modulation index. The whole chip consumes 20mW from a 1.2V supply voltage, where the FSK/MSK demodulator core circuit only consumes 6mW.7585979 bytesapplication/pdfen-US毫米波互補式金氧半場效電晶體相位陣列接收機低雜訊放大器雙閘極混波器主動式旋相器連續相位頻率鍵移最小鍵移注入式解調變器Millimeter-WaveCMOSPhased-Array ReceiverLow Noise Ampli er (LNA)Dual-gate MixerActive Phase ShifterContinuous Phase Frequency Shift Key- ing (CPFSK)Minimum Shift Keying (MSK)Injection-locked Demodulator應用於高速資料傳輸接收機之毫米波互補式金氧半場效電晶體電路與系統架構設計CMOS Millimeter-Wave Circuits and Architecture Design Techniques for High Date Rate Receiverthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/256841/1/ntu-99-D93943011-1.pdf