臺灣大學: 電子工程學研究所呂良鴻詹子平Chan, Tzu-PingTzu-PingChan2013-04-102018-07-102013-04-102018-07-102010http://ntur.lib.ntu.edu.tw//handle/246246/257091隨著 CMOS 製程技術的發展和尺寸減小，近年來對高速和高整合密度之超大型積體電路的需求與日俱增。所以本篇論文將介紹高速延遲鎖定迴路的設計與實作。然而因為相位偵測器與充電泵的緩慢動作，典型延遲鎖定迴路的操作頻率徹底地被限制了。並且充電泵的電流不匹配也造成顯著的靜態相位誤差。此外由於輸入時脈雜訊造成輸出的時脈誤差放大也降低了系統的效能。本論文中為了增加系統速度並且改進時脈誤差，所推薦的架構之設計考量與實現將被提出。 首先，使用 0.18-μm CMOS 製程的高速延遲鎖定迴路架構被提出。透過在相位偵測器之前使用除頻器，相位偵測器和充電泵的工作頻率可以被減輕。而且因為利用除頻器產生的四相位訊號，在控制路徑上的漣漪可以降低，時脈誤差性能可改善。抖動轉移函數(JTF)的分析以及部分電路的設計會提出說明。所以高速延遲鎖定迴路得以實現，測量結果也被闡述。 接著，包含多頻帶的延遲線技巧的延遲鎖定迴路被呈現。由於降低的延遲線增益架構，控制路徑的漣漪偶合的雜訊可以被顯著地壓抑並且得到較好的時脈誤差反應。此外，放置在相位偵測器之前的除頻器可以增加偵測器的有效偵測範圍因此諧波鎖定的問題可以避免。此延遲鎖定迴路使用 0.18-μm CMOS 製程實作並且加以量測。With the evolution and scaling down of CMOS technologies, the demand for high-speed and high integration density VLSI system has recently grown exponentially. Hence, this thesis illustrates the implementation of the high speed delay-locked loops (DLLs). However, the operating frequency of typical DLL is drastically limited by phase detector and charge pump because of their slow movement. Besides, the current mismatch of charge pump will result in a significant static phase error. Moreover, the output’s jitter peaking due to input clock noise also degrades the system performance. In this thesis, design considerations and realization about the proposed architectures are presented in order to increase the system speed and improve the jitter performance. Firstly, a high-speed delay-locked loop architecture implemented with 0.18-μm CMOS process is presented. Using the frequency divider in front of the phase detector, the operating frequency of phase detector and charge pump can be alleviated. Furthermore, using the quadratic-phase generated by the divider, the ripple on controlled-line can be lowered and the jitter performance can improve. The analysis of jitter transfer function (JTF) and building block circuit design are illustrated. Therefore, a high-speed DLL is realized and the measurement results are also described. In the second work, a DLL incorporating multi-band delay line technique is proposed. With a reduced KVCDL architecture, the noise amount coupling from the controlled-line ripple can be suppressed evidently and obtain better jitter behavior. Moreover, the divider circuit, which places before the phase detector, can enlarge the equivalent detectable range of the PD and the harmonic locking problem can be avoided. Implemented with standard TSMC 0.18-μm CMOS process, a 2.8-GHz low-jitter DLL is proposed and the measurement results are also demonstrated.1969575 bytesapplication/pdfen-US延遲鎖定迴路高速低時脈誤差delay-locked loophigh-speedlow-jitterhttp://ntur.lib.ntu.edu.tw/bitstream/246246/257091/1/ntu-99-R96943136-1.pdf