Che-Fu LiangSy-Chyuan HwuSHEN-IUAN LIU2018-09-102018-09-102008-0500189200http://scholars.lib.ntu.edu.tw/handle/123456789/342648https://www.scopus.com/inward/record.uri?eid=2-s2.0-42649138885&doi=10.1109%2fJSSC.2008.920322&partnerID=40&md5=bb47d339fac0eab8e9459dd4c67405bfA jitter-tolerance-enhanced 10 Gb/s clock and data recovery (CDR) circuit is presented. The proposed architecture cascades 2 half-rate CDRs with different loop bandwidth to relax the design bottleneck and the predicted jitter tolerance can be enhanced without sacrificing the jitter transfer. By using a gated digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector may reduce the cost of this architecture and achieve a wide linear range. This CDR circuit has been fabricated in a 0.13 μm CMOS technology and consumes 60 mW from a 1.5 V supply. It occupies an active area of 0.36 mm 2. The measured rms jitter is 0.96 ps and the peak-to-peak jitter is 7.11 ps for a 10 Gb/s 27 - 1 PRBS. The measured bit error rate for a 10 Gb/s 27 - 1 PRBS is less than 10-12. © 2006 IEEE.Bandwidth; Bit error rate; CMOS integrated circuits; Oscillators (electronic); Clock and data recovery; Jitter tolerance; Jitter transfer; Jitterjournal article10.1109/JSSC.2008.9203222-s2.0-42649138885WOS:000255354300017