Chang Y.-TChen H.-YHSIN-CHIA LU2021-09-022021-09-022017https://www.scopus.com/inward/record.uri?eid=2-s2.0-85032827176&doi=10.1109%2fRFIT.2017.8048247&partnerID=40&md5=0a47361b5c2429e5bd9c3c91af63994dhttps://scholars.lib.ntu.edu.tw/handle/123456789/580849In this paper, we propose a high linearity CMOS sub-harmonic I/Q demodulator at V-band using CMOS 90 nm process. We adopt frequency doubler to double input LO frequency and use transformer to couple 2LO signal to mixer core. In addition, transformer coupling is used to replace stacked transistors to improve linearity. Cross couple pair is also utilized as active load to enhance conversion gain. The measured peak conversion gain is-7.9 dB under LO power of 9 dBm. The IP1dB and nP3 are 0 dBm and 9 dBm, respectively. The total DC power consumption is only 13.68 mW for 1.2 V supply voltage. To our best knowledge this demodulator has the best linearity at V-band. ? 2017 IEEE.CMOS integrated circuits; Harmonic analysis; Radio waves; Conversion gain; cross couple pair; DC power consumption; Doublers; Stacked transistors; Subharmonics; Supply voltages; Transformer coupling; Demodulatorsconference paper10.1109/RFIT.2017.80482472-s2.0-85032827176