Lai, Y.-K.Y.-K.LaiLai, Y.-L.Y.-L.LaiLiu, Y.-C.Y.-C.LiuLIANG-GEE CHEN2018-09-102018-09-10199800983063https://www.scopus.com/inward/record.uri?eid=2-s2.0-0032141487&doi=10.1109%2f30.713173&partnerID=40&md5=81fad4ddb0def7f536ffe4fadc5e5633http://scholars.lib.ntu.edu.tw/handle/123456789/337835This paper describes the VLSI implementation with two-dimensional (2-D) data-reuse architecture for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates. © 1998 IEEE.Algorithms; Computer architecture; Shift registers; Block matching algorithm (BMA); Motion estimators; Processing element (PE) arrays; Two-dimensional data reuse; VLSI circuitsjournal article10.1109/30.7131732-s2.0-0032141487