Test set compaction for combinational circuits

Dept. of Electr. Eng., National Taiwan Univ.Chang, Jau-ShienJau-ShienChangLin, Chen-ShangChen-ShangLin2007-04-192018-07-062007-04-192018-07-061992-11http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032321application/pdf484377 bytesapplication/pdfen-USTest set compaction for combinational circuitsjournal article10.1109/ATS.1992.224429http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032321/1/00224429.pdf