Dept. of Electr. Eng., National Taiwan Univ.Chen, S.-S.S.-S.ChenChen, J.-J.J.-J.ChenTsai, C.-C.C.-C.TsaiSAO-JIE CHEN2018-09-102018-09-10200013502387http://www.scopus.com/inward/record.url?eid=2-s2.0-0033346494&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/289911A pin grid array (PGA) package router is described. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to-pin nets on one or more layers. This router consists of three phases: layer assignment, topological routing and geometrical routing. Examples tested on a windows-based environment show that our router is efficient and can complete the routing task with less substrate layers. Compared to manual routing, this router has a user-friendly graphic interface and can be applied practically to industrial strength VLSI packaging. © lEE, 1999.application/pdf827176 bytesapplication/pdfBoundary conditions; Electronics packaging; Graphical user interfaces; Integrated circuit testing; Interconnection networks; Routers; Substrates; Pin grid array (PGA) packages; Integrated circuit layoutconference paper10.1049/ip-cdt:199907972-s2.0-0033346494