劉深淵臺灣大學：電子工程學研究所張湘輝Chang, Hsiang-HuiHsiang-HuiChang2007-11-272018-07-102007-11-272018-07-102004http://ntur.lib.ntu.edu.tw//handle/246246/57431隨著CMOS製程技術進步，使得更多數位電路整合在一系統中，同時也提升這些數位電路的操作速度。較高的操作速度將會縮短時間安全範圍。而造成時間上的相位誤差和時脈抖動將使得同步這些數位電路變得更困難。 延遲鎖相迴路已廣泛地被運用在解決時間的相位誤差和時脈的抖動問題。 相對於鎖相迴路，延遲鎖相迴路有著無條件穩定、快速鎖定優點。而且，因為延遲鎖相迴路使用的壓控延遲線並不會累積雜訊。所以，延遲鎖相迴路也提供較佳的抖動輸出。如果頻率合成非必要的需求，在處理同步問題時，延遲鎖相迴路是較佳的選擇。但是，傳統延遲鎖相迴路卻有著較小操作頻率範圍、缺乏頻率合成弁遄B壓控延遲線中相位間不匹配、及壓控延遲線的雜訊不能被壓制等缺點。使得延遲鎖相迴路的應用範圍受到限制。本論文主題之研究內容，在於如何解決傳統延遲鎖相迴路之限制，並將這些方法加以實現，以提升介面電路的性能及應用性。 在此論文中提出了一個全數位循環控制式延遲鎖相迴路以解決延遲鎖相迴路操作頻率範圍太小及設計時易受製程參數影響之方法。所提出的循環控制式延遲單元可以增加操作頻率範圍達256倍。因此，延遲單元個數和操作頻率設計上的限制可以被降低。 論文中也提出一數位校正電路以解決因元件間不匹配所造成的相位誤差之問題。理論上，利用所提出之數位校正電路，多相位輸出間的相位誤差可以減少至1.2倍量化誤差。 最後，論文中提出一以延遲鎖相迴路為基礎的時脈及資料回復電路，藉以達到低抖動和低錯誤率的弁遄C同時也克服傳統不能實現寬頻帶操作之限制。平均移轉相位技術也提出解決因元件間不匹配所造成的相位誤差之方法。同時也提出一相位偵測器來減低對輸出波形之脈衝寬度的依賴。 論文中所提出之三種延遲鎖相迴路，將可使延遲鎖相迴路於不同應用中提供更佳的可行性及可靠度。Modern CMOS techniques can not only integrate many digital circuits into a system, but also raise the operating clock frequency of the digital systems. However, the higher operating clock will decrease the timing margin for high-performance digital systems. As the timing margin is tight, the timing skews and jitters would make it difficult to synchronize among IC modules. Delay-locked loops （DLLs）have been widely used to minimize timing skews and jitters of the clock signals. The DLLs benefit from the unconditional stability, fast locking time and better jitter performance compared with the PLLs. If no frequency synthesis is needed, the DLLs are preferred for the purpose of synchronization. However, various intrinsic problems exist in a conventional DLL such as narrow operation frequency range, harmonic locking, lack of frequency synthesis function, mismatch among delay stages, and unsuppressed VCDL noise. To develop the solutions for the limitations existing in the conventional DLL and realize is the object of this dissertation. Firstly, a wide-range and fast-locking all-digital DLL is presented to resolve the narrow operating range problem. The cycle-controlled delay unit could enlarge the operating frequency range of the proposed DLL by a factor of 256 without decreasing timing resolution. The trade-off between the number of delay stages and the operating frequency range can be removed in the proposed all-digital DLL. Secondly, a digital calibration circuit is presented to provide another way to average the mismatch-induced timings in the digital domain when the DLL operates at 2GHz. With the proposed digital calibration circuit, the mismatch-induced timing error among multiphase clocks can be reduced to be less than 1.2X quantization error theoretically. A DLL-based CDR is presented to resolve the jitter accumulated problems and so achieves both low jitter and multi data rate operation. The MASDLL provides the function of the integer multiplication frequency synthesis to extend the operating frequency range. The shifted-averaging technique is also proposed to average the mismatch-induced timing error among delay stages in the analog domain. A duty-cycle-insensitive phase detector can mitigate the dependency on clock duty cycle variations. Three DLLs proposed in this dissertation allow more flexibility or more reliable performance for utilizing DLLs in various applications.Table of Contents Acknowledgments I Abstracts ………………………………………………………………..V Table of Contents VII List of Figures IX List of Tables XII Chapter 1 Introduction 1 1-1 Motivation 1 1-2 Organization 5 Chapter 2 Design Considerations and Procedures of the basic DLL 7 2-1 Basic analysis of the DLL 7 A. Type I DLL 7 B. Type II DLL 11 S-domain 11 Z-domain 15 2-2 Design considerations of the basic building blocks in the DLL 19 A. VCDL 19 B. PD 21 C. CP 22 2-3 Design procedures of the basic DLL 25 2-4 An example of design the basic DLL 25 A.VCDL 25 B. Behavior simulations 26 C. PD and CP design 27 D. Closed loop simulations 28 E. Experimental results 30 2-5 Summary 32 Chapter 3 A Wide-Range and Fast-Locking All-Digital Cycle-controlled Delay-Locked Loop 33 3-1 INTRODUCTION 33 3-2 Limitations of the conventional digital DLL 35 3-3 The architecture of the proposed DLL 38 3-4 Circuit description 41 A. Cycle-controlled delay unit (CCDU) 41 B. Hierarchical delay unit (HDU) 42 C. Two-step SAR controller 45 D. Edge combiner 47 3-5 Experimental results 48 3-6 Summary 52 Chapter 4 A 2GHz Precise Multiphase Delay-Locked Loop with a Digital Calibration circuit 55 4-1 Introduction 55 4-2 Proposed digital calibration algorithm 57 4-3 Circuit Design 61 A. Overall structure 61 B. Delay cell and DCOB 63 C. Digital calibration circuit 65 D. PD 71 E. Start controlled circuit 73 4-4 Post-layout simulated results 76 4-5 Summary 79 Chapter 5 Low Jitter and Multi-rate Clock and Data Recovery Circuit using a MSADLL for chip-to-chip interconnection 81 5-1 Introduction 81 5-2 The proposed CDR architecture 83 A. Operation of the CDR 83 B. Analysis of the CDR stability 86 C. Analysis of the lock time 89 5-3 Circuit description 90 A. Multiplying shifted-averaging DLL (MSADLL) 90 B. Duty-cycle-insensitive phase detector 97 C. Programmable delay line 99 D. Rate-detection circuit 101 5-4 Experimental results 103 5-5 Summary 108 Chapter 6 Conclusions 111 6-1 Conclusions 111 6-2 Future work 112 Bibliography 115 Publication List 119en-US操作頻率鎖相迴路壓控延遲線延遲鎖相迴路VCDLPLLOperating frequencyDLLthesis