顧孟愷臺灣大學:資訊工程學研究所劉奕廷Liu, Yi-TingYi-TingLiu2010-05-172018-07-052010-05-172018-07-052009U0001-2807200919145200http://ntur.lib.ntu.edu.tw//handle/246246/183369在這篇論文，我們提出了基於一種先進動態情報排程的快速收斂排程方法用在低密度奇偶校驗編碼之解碼器。另外，我們設計了是用於此方法的硬體架構適用於IEEE 802.16e，也是大家所知的全球互通微波存取。從電腦模擬結果顯示，提出的方法跟水平階層解碼演算法比約減少解碼次數46.92%在信號雜訊比為1分貝之下和最大解碼次數設為20。另外，我們方法的位元錯誤率也只有可忽略的退步。我們實作提出演算法於賽靈思公司的元件可編程邏輯閘陣列版上驗證其正確性。實作結果得知額外的硬體開銷跟記憶體使用很小。因為較低的解碼次數，整個系統的吞吐量也提高許多。跟原本動態情報排程設計比較，我們提出的演算法之複雜度是低得多，而可以在硬體上很容易實作。In this thesis, we propose the fast convergence scheduling method based on the novel technique named Informed Dynamic Scheduling for low-density parity-check code decoder. In addition, we design the hardware architecture to fit with the proposed method applied to IEEE 802.16e standard which is known as WiMAX. From the computer simulation result, the proposed method decreases the decoding iteration up to 46.92% compared with the horizontal layer decoding algorithm when Signal-to-noise ratio is 1dB and the maximum decoding iteration is 20. Furthermore, the BER performance of our method has only small degradation which can be ignored. We also implement the proposed algorithm on Xilinx FPGA board to verify the correctness. The implementation result shows that the extra hardware cost and memory usage is small. The total system throughput also improves because of the lower decoding iterations. Compare with the origin Informed Dynamic Scheduling method, the complexity of our proposed algorithm is much lower that can be implemented on the hardware easily.中文摘要 iBSTRACT iiONTENTS iiiIST OF FIGURES viIST OF TABLES viiihapter 1 Introduction 1.1 Digital Communication System Overview 1.2 Low-Density Parity-Check (LDPC) Code 2.2.1 Introduction to LDPC Code 2.2.2 Representation of LDPC Code 3.2.3 Quasi-Cyclic LDPC Code (QC-LDPC) 6.3 Motivation of the Thesis 7.4 Thesis Organization 8hapter 2 LDPC Decode Algorithm and Schedule 9.1 Overview of LDPC Decode 9.2 Decode Algorithm 12.2.1 Sum-Product Algorithm 12.2.2 Min-Sum Algorithm 14.3 Decode Schedule 14.3.1 Two Phase Schedule 15.3.2 Horizontal Layer Schedule 16.4 LDPC Code Decode Performance 19.4.1 LDPC Code for IEEE 802.16e Standard 19.4.2 Software Simulation Result 21.4.3 Fixed Point Simulation Result 24hapter 3 Proposed Fast Convergence LDPC Decode Algorithm 27.1 Informed Dynamic Schedule (IDS) 27.1.1 Node-wise Residual Belief Propagation 27.1.2 Performance and Complexity Analysis 30.2 Low Complexity and Fast Convergence LDPC Decode Algorithm Based on IDS 32.2.1 Overview of Proposed Algorithm 32.2.2 Conditional Layer Propagation Algorithm 33.2.3 The Method to Update Row Decision Vector 36.3 Comparison between IDS and CLPA 39hapter 4 Hardware Architecture Design 41.1 Overview of Proposed Hardware Architecture 41.2 Memory Block 42.3 Row Operation Unit 44.4 Decision Update Unit 45.5 I/O Controller 46.6 Control Unit 47.7 System Schedule Scheme 49hapter 5 Software Simulation and Hardware Implementation 51.1 Software Simulation Results 51.1.1 Decode Iteration 52.1.2 BER Performance 54.2 FPGA Evaluation Platform 55.3 FPGA Design Flow 56.4 FPGA Implementation Result 59hapter 6 Conclusion and Future Work 61.1 Conclusion 61.2 Future Work 62EFERENCE 63application/pdf2484383 bytesapplication/pdfen-US低密度奇偶校驗編碼快速收斂解碼器全球互通微波存取動態情報排程錯誤更正碼LDPCFast ConvergenceDecoderWiMAXInformed Dynamic SchedulingChannel Codingthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/183369/1/ntu-98-R96922096-1.pdf