A high-speed conditional carry select (CCS) adder circuit with a successively incremented carry number block (SICNB) structure for low-voltage VLSI implementation

Huang Y.-MJAMES-B KUO2023-06-092023-06-09200010577130https://www.scopus.com/inward/record.uri?eid=2-s2.0-0034292708&doi=10.1109%2f82.877148&partnerID=40&md5=60368c9cc9dc32823297b4bba008b978https://scholars.lib.ntu.edu.tw/handle/123456789/632459This paper reports a conditional carry select (CCS) adder circuit with a successively-increniented-carry-nurnber block (SICNB) structure for low-voltage VLSI implementation. Owing to the successively-incremented-carry-number block (SICNB) structure, the new 16-bit SICNB CCS adder provides a 37% faster speed as compared to the conventional conditional carry select adder based on the SPICE results. © 2000 IEEE.Carry select adders; High-speed; Low-voltage; Multipliers[SDGs]SDG7Conditional carry select adder circuit; Successively incremented carry number block structure; Computer simulation; Electric power supplies to apparatus; Electric waveforms; Gates (transistor); Logic circuits; Logic design; MOS devices; VLSI circuits; AddersA high-speed conditional carry select (CCS) adder circuit with a successively incremented carry number block (SICNB) structure for low-voltage VLSI implementationjournal article10.1109/82.8771482-s2.0-0034292708